Tandy 1000 Technical Reference Manual

Tandy 1000
inter
8259AJ8259A-2/8259A-8
Technical Reference Manual
THECASCADEBUFFE~COMPARATOR
This function block stores and compares the IDs of all
8259A's used in the system. The associated three 1/0
PinS (CASO-2) are outputs when the 8259A is used as a
master and are inputs when the 8259A is used as a
slave. As a master, the 8259A sends the 10 of the inter-
rupting slave device onto the CASO-2 lines The slave
thus selected will send its preprogrammed subroutine
address onto the Data Bus during the next one or two
consecutive INTA pulses (See section "Cascading the
8259A" )
INTERRUPT SEQUENCE
The powerful features of the 8259A in a microcomputer
system are its programmability and the interrupt routine
addressing capability. The latter allows direct or indirect
lumping to the specific interrupt routine requested
without any polling of the interrupting devices. The nor-
mal sequence of events during an Interrupt depends on
the type of CPU being used.
The events occur as follows In an MCS·80/85 system
lOne or more of the INTERRUPT REQUEST lines
IIR7-0) are raised high, setting the corresponding IRR
bit(s)
2 The 8259A evaluates these requests, and sends an
tNT to the CPU, If appropriate
3. The CPU acknowledges the INT and responds with an
INTA pulse
4. Upon receiving an INTA from the CPU group, the
highest priority ISR bit is set, and the corresponding
IRR bit IS reset The 8259A will also release a CALL in·
struct,on code (110011011 onto the 8·blt Data Bus
'''rough ItS 07-0 pins
5. This CALL instruction will Initiate two more INTA
pulses to be sent to the 8259A from the CPU group
6. These two INTA pulses allow the 8259A to release its
preprogrammed subroutine address onto the Data
Bus The lower 8-blt address 's released at the fIrst
INTA pulse and and the higher 8-blt address IS re-
leased at the second INTA pulse
7. ThiS completes the 3·byte CALL Instruction released
by the 8259A In the AEOI mode the ISR bit is reset at
the end of the thIrd iNTA pulse. OtherWise, the ISR bit
remains set until an appropriate EOI command is
Issued at the end of the Interrupt sequence
The events occu rrtng In an IAPX 86 system are the same
until step 4
4. Upon receiving an INTA from the CPU group, the high-
est pfloflty ISR bit IS set and the corresponding IRR
bit is reset The 8259A does not drive the Data Bus
dUring tn,s cycle
5. The ,APX 86.'0 will Initiate a second INTA pulse
Dunng 'hiS pulse. the 8259A releases an 8-bit pOinter
onto the Data Bus wnere It IS read by the CPU
6 fh,s completes the Interrupt cycle. In the AEOI mode
Ine ISR bit IS reset at the end of the second INTA
pulse OtherWise. the ISR bit remains set until an
appropnate EOI command is Issued at the end of the
Interrupt subroutine
If no interrupt request is present at step 4 of either
sequence (i.e., the request was too short in duration) the
8259A will issue an interrupt level 7. Both the vectoring
bytes and the CAS lines will look like an interrupt level 7
was requested.
Figure 4c. 8259A Block Diagram
CASCADE r
LINES
Figure 5. 8259A Interface to Standard
System Bus
2-124

Tandy 1000 Specifications

General

Processor	Intel 8088
Processor Speed	4.77 MHz
RAM	128 KB (expandable to 640 KB)
Operating System	MS-DOS 2.11
Manufacturer	Tandy Corporation
Release Year	1984
Storage	Single or double 5.25" floppy disk drive (360 KB), optional hard drive
Sound	Tandy 3-voice sound
Ports	Parallel, Serial
Graphics	CGA (Color Graphics Adapter)
Graphics Modes	320x200, 640x200