Tandy 1000 Technical Reference Manual

Tandy 1000
intel
READING THE 8259A STATUS
Technical Reference Manual
8259A18259A-2/8259A-8
EDGE AND LEVEL TRIGGERED MODES
The input status of several internal registers can be read to
update the user information on the system. The following
registers can be read via OCW3 (IRR and ISR or OCW1
[IMRl)
Interrupt Request Register (lRR): B-bit register which con-
tains the levels requesting an interrupt to be acknowl-
edged. The highest request level is reset from the IRR
when an Interrupt IS acknowledged. (Not affected by IMR.)
In-Service Register (ISR): B-blt register which contains the
priority levels that are being serviced. The ISR is updated
when an End of Interrupt Command IS issued
Interrupt Mask Register: B-bit register which contains the
interrupt request lines which are masked
The IRR can be read when, prior to the RD pulse, a Read
Register Command IS issued with OCW3 (RR = 1, RIS 0)
The ISR can be read when, prior to the RD pulse. a Read
Riglster Command is Issued with OCW3 (RR 00 1, RIS = 1)
T
ere IS no need to write an OCW3 before every status
re d ooeration, as long as the status read corresponds
with the prevIous one; I.e, the B259A "remembers
whether the IRR or ISR has been previously selected by
the OCW3. This IS not true when poll IS used
After Initialization the B259A IS se~ to IRR
For reading the IMR, no OCW3,s needed. The output data
bus will contain the IMR whenever R1S IS active and AO 1
(OCW1)
Polling Gvemdes status read when P 1 RR = 1 In OCW3
This mode IS programmed using bit 3 in ICW1.
If LTIM = '0', an interrupt request will be recognized by a
low to high transition on an IR input. The IR input can re-
main high without generating another interrupt
If LTIM = '1', an interrupt request will be recognized by a
high' level on IR Input, and there is no need for an edge
detection. The interrupt request must be removed before
the EOI command is issued or the CPU interrupt is enabled
to prevent a second interrupt from occurring
The priority cell diagram shows a conceptual circuit of the
level sensitive and edge sensitive input circuitry of the
B259A. Be sure to note that the request latch is a transpar-
ent D type latch
In both the edge and level triggered modes the IR inputs
must remain high until after the falling edge of the first
INTA. If the IR Input goes low before this time a DEFAULT
IR7
will occur when the CPU acknowledges the Interrupt
This can be a useful safeguard for detecting Interrupts
caused by SPUriOUS noise glitches on the IR inputs. To im-
plement this feature the IR7 routine is used for "clean up"
Simply executing a return Instruction, thus Ignoring the
interrupt. If IR7 IS needed for other purposes a default IR7
can stili be detected by reading the ISR A normal IR7
Interrupt will set the corresponding ISR bit, a default IR7
won't. If a default IR7 routine occurs during a normal IR7
routine, however. the ISR will remain set. In this case It is
necessary to keep track of whether or not the IR7 routine
was previously entered If another IR7 occurs It IS a
default
IR~
•
'i'-----€t:-cc-_ --_-_~-_ -\~~&--J! /
~,
\'--_\~-~--+--'~ /
808618088
VS.S.'8.SS
LATCH
ARMED
EARLIEST IF!
CA."" BE REMOVED
Figure 10, IR Triggering Timing Requirements
2-132
LATCH'
ARMED

Tandy 1000 Specifications

General

Processor	Intel 8088
Processor Speed	4.77 MHz
RAM	128 KB (expandable to 640 KB)
Operating System	MS-DOS 2.11
Manufacturer	Tandy Corporation
Release Year	1984
Storage	Single or double 5.25" floppy disk drive (360 KB), optional hard drive
Sound	Tandy 3-voice sound
Ports	Parallel, Serial
Graphics	CGA (Color Graphics Adapter)
Graphics Modes	320x200, 640x200