Tandy 1000
inter
8237A/8237~4/8237~5
Table 1. Pin
Description
Technical Reference Manual
Symbol
Vee
Vss
ClK
CS
RESET
READY
HLDA
DREQO-DREQ3
DBD-DB7
Type H
......
nd
Function
P_er:
+ 5 volt supply.
Ground: Ground.
CIocll Input: Clock Input
controls
the
Internal
operations
of
the
8237A and
its
rate
of
data trans·
fers. The Input may be driven at up
to
3 MHz
for
the standard
8237A
and up
to
5 MHz
for
the 8237A·5.
Chip
S.lect:
Chip Select is
an
ac-
tive low Input used
to
select the
8237A as
an
I/O device during the
Idle cycle. This allows
CPU
com-
munication on the data bus.
R
...
t: Reset is
an
active high In·
put
which clears the Command,
Status, Request and Temporary
registers.
It
also
clears
the
f1rsUlast fIIplflop and sets the
Mask register. Following a Reset
the
device is in the Idle cycle.
RNdy:
Ready is
an
input used
to
extend the memory read and write
pulses from the
8237A
to
accom-
modate slow memories
or
I/O
per-
ipheral devices. Ready must not
make
transitions
during
its
speci·
fied setup/hold time.
Hold
Acknowledge:
The
active
high Hold Acknowledge
Irom
the
CPU indicates that it has relin-
quished control
of
the system
busses.
OMA Reque.t: The DMA Request
lines are individual asynchronous
channel request
inputs
used by pe-
ripheral
circuits
to
obtain DMA
service. In fixed Priority,
DREQO
has
the
highest
priority
and
DREQ3 has the lowest priority. A
request Is generated
by
activating
the
DREQ
line
of
a channel. DACK
will
acknowledge the recognition
of
DREQ
signal. Polarity of
DREQ
is
programmable. Reset intializes
these lines to active high.
DREQ
must
be maintained until the corre-
sponding DACK goes active.
I/O
O.t.
Bue: The Data Bus tines are
bidirectional
three·state
signals
connected
to
the system data bus.
The
outputs
are enabled In the Pro·
gram
condition
during the
I/O
Read
to
output
the contents
of
an
Ad·
dress register, a Status register,
the Temporary register or a Word
Count
register
to
the CPU. The out-
puts
are disabled and the
inputs
are read during
an
I/O Write cycle
when
the
CPU
Is programming the
8237A control registers. During
DMA cycles the most
significant
8
bits
of
the address are
output
onto
I
the data bus
to
be strooeo Into
an
external latch
by
ADSTB. In
memo
2-89
Symbol
lOR
lOW
EOP
AO-A3
Type H
.....
•
nd
Function
ory·to·memory
operations, data
from the memory comes
Into
the
8237A on
the
data bus during the
read·from-memory transfer. In the
wrlte-tOomemory transfer, the data
bus
outputs
place the data
Into
the
new memory location.
I/O
I/O
R.ad:
I/O Read Is a bldlrec·
tlonal active low three-atate line. In
the Idle cycle,
It
Is
an
Input control
elgnal used
by
the
CPU
to
read the
control
registers. In the Active cy-
cle, It Is
an
output
control signal
used by the 8237A
to
access data
from a peripheral during a DMA
Write transfer.
I/O I/O
Writ.:
I/O Write is a bidirec-
tional
active
low three-state line. In
the Idle cycle,
It
is
an
Input
control
signal used by the
CPU
to load In-
formation
Into
the 8237A.ln the Ac-
tive cycle, It
Is
an
output
control
signal used by the
8237
A
to
load
data
to
the
peripheral during a
DMA Read transfer.
I/O
End
01
Proce
••
: End
of
Process Is
an
active
low
bidirectional signal.
Information concerning the com-
pletion
of
DMA services is avail-
able at
the
bidirectional
EOP
pin.
The 8237A allows
an
external slg·
nal
to
terminate
an
active DMA
service. This Is accomplished by
pulling the EOP Input low with
an
external EOP signal. The 8237A al·
so generates a pulse when the ter·
mlnal
count
(TC)
for
any channel
Is
reached. This generates
an
EOP
~al
which
Is
output
througtl..!!!.e
EOP
Line. The reception
of
EOP,
either Internal
or
external, will
cause the 8237A
to
terminate the
service, reset the request, and,
if
Autoinitialize Is enabled, to
write
the base registers to the current
registers
of
that channel. The mask
bit
and
TC
bit
in the status word
will be set
for
the currently active
channel by
EOP
unless the channel
Is programmed
for
Autoinitialize. In
that case,
the
mask bit remains
un-
changed. During memory·to·memory
transfers, EOP will
be
output when
the
TC
lor
channel 1 occurs.
EOP
should be tied high with a pull·up
resistor If
It
Is
not
used to prevent
erroneous end
of
process Inputs.
I/O
Addr
••
e:
The
four
least significant
address lines are bidirectional
three-state signals. In the Idle
cy-
cle they are
inputs
and are used
by
the
CPU
to
address the register
to
be
loaded or read.
In
the Active
cycle they are
outputs
and provide
the
lower
4
bits
of
the
output
address.
AFN·OO7890
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