Tandy 1000
MC6845
to
the
reference. It
is
programmed
in
character row times.
Interlace Mode Register
(RB)
- This 2 bit write-only
register controls
the
raster scan mode
(see
Figure 11).
When bit 0 and
bit
1 are reset,
or
bit 0
is
reset and bit 1
set,
the
non·
interlace raster scan
mode
is
selected.
Two
interlace modes are available. Both are interlaced 2 fields
per frame. When bit 0
is
set and bit 1
is
reset, the interlace
sync raster scan
mode
is
selected. Also when bit 0 and bit
1 are set,
the
interlace sync and video raster scan mode
is
selected.
Maximum Scan Line Address Register (R9)
- This 5
bit write-only register determines
the
number
of scan lines
per character row including spacing. The programmed
value
is
a max address and
is
one
less
than
the
number
of
scan lines.
OTHER REGISTERS
Cursor
Start
Register (RIO) - This 7 bit write-only
register
controls
the
cursor
format
(see Figure 10). Bit 5
is
the
blink timing
control.
When bit 5
is
low, the blink
frequency
is
1/16
of
the
vertical field rate, and
when
bit
5
is
high,
the
blink frequency
is
1/32
of
the
vertical field
rate. Bit 6
is
used
to
enable a blink. The cursor
start
scan
line
is
set by
the
lower 5 bits.
Cursor End Register
(R
11) - This 5
bit
write-only
register sets the cursor
end
scan line.
Start
Address Register
(H
& U (R12, R13) -
Start
Address Aegister
is
a 14 bit write-only register which
determines the first address
put
out
as a refresh address
after vertical blanking_ It consists of an B bit lower
register, and a 6 bit higher register.
Light Pen Register
(H
& U (R16,
R17)
- This 14
bit
read-only register
is
used
to
store
the
contents
of
the
Address Aegister
(H
&
L)
when
the
LPSTB input pulses
high. This register consists
of
an 8 bit
lower
and 6 bit
higher register.
Cursor Register
(H
&
L)
(R14, R15) - This 14 bit
read/write register stores
the
cursor location. This register
consists of an 8 bit lower and 6 bit higher register.
CURSOR
The
Cursor
Start
and End Registers allow a cursOf of
up
to
32
scan lines in height
to
be placed on any scan lines
of
the
character block as shown in Figure 10. Using Bits 5
& 6
of
the
Cursor
Start
Aegister,
the
cursor
is
programmed
with
blink periods of 16 or
32
times
the
field
period. Optional non·blink and non-display modes can
also be selected. When an external 2X blink
on
characters
is
required, it
may
be necessary
to
perform cursor blink
externally
as
well
so
that
both
blink rates are
synchronized. Note
that
an invert/non-invert cursor
is
easily implemented by programming
the
CRTC for
blinking cursor
and
externally inverting
the
video signal
with an exclusive-OR.
The
cursor
is
positioned by changing
the
contents
of
registers R14 and A15. The cursor
can
be placed at any
of
16K character positions,
thus
facilitating hardware paging
and scrolling through memory
without
loss
of
the
cursor's
original position.
Technical Reference Manual
INTERLACE/NON-INTERLACE
DISPLAY MODES
An illustration
of
the
3 raster scan modes of
operation
is
shown
in
Figure 11. Normal sync mode
is
non-interlace.
In
this mode, each
scan
line
is
refreshed
at
the vertical
field rate (e.g.,
50
or
60
Hz).
Frame
time
is
divided into
even and
odd
alternating fields.
The
horizontal and
vertical timing relationship results
in
the
displacement
of
scan lines
in
the
odd
field
with
respect
to
the
even field.
When the same information
is
painted
in
both
fields, the
mode
is
called
"Interlace
Sync;"
this
is
a useful mode for
enhancing readability
by
filling in a character. When
the
even lines
of
a
character
are displayed
in
the
even field
and
the
odd
lines
in
the
odd
field,
the
mode
is
called
"Interlace
Sync
and
Video."
This last
mode
effectively
doubles the character density
On
a
monitor
of a given
bandwidth. The disadvantage
of
both interlace modes
is
an apparent flicker
effect,
which can be reduced by
careful monitor design.
There are restrictions on
the
programming
of
CATC
registers for interlace
operation:
1)
Horizontal total
character
count,
N
ht
must be
odd
(i.e., an even
number
of character times)
21
For Inttrlace
Sync
and Video
mode
only,
the
max
scan line address, Nsl, must be
odd
(i.e., an even
number
of
scan linesl
3) For Interlace
Sync
and Video
mode
only,
the
Vertical Displayed Total characters
must
be even.
The programmed number, Nvd' must be
one-half
the
actual number required.
4)
For
Interlace
Sync
& Video mode only,
the
Cursor
STAAT and Cursor End Aegisters must
both
be
even or
both
odd_
LIGHT
PEN
The
contents
of
the
CATC Address
Counter
are
strobed into A16/A17 Light Pen Aegisters on
the
next
high
to
low CLK transition afterLPSTB goes high.
In
most
systems,
the
light pen signal would also cause a processor
interrupt
routine to read A16/A17. Slow light pen
response requires the processor software
to
modify
the
captured address read from A16/A 17 by a calibration
factor.
PROGRAMMING CONSIDERATIONS
Initialization - Aegisters
RO-A
15
must
be initialized
after power
is
turned
on,
The
processor normally loads
the
CATC registers sequentially from a firmware table.
Henceforth,
AO-A
11
are
not
changed
in
most
systems.
The
6800
program in Table 3 and Figure 12 shows a
typical CATC initialization.
Hardware Scrolling - Aegisters A12/A
13
contents
determine which
memory
location
is
the
first displayed
character on
the
screen. Since
the
CATC Linear Address
Generator
counts
from this beginning
count,
the
displayed
portion
of
the
screen
may
be a window
on
any
continuous
string of characters
within
a 16K block
or
refresh
memory.
By
centering
the
A12/A 13 pointer
in
the
middle
of
the
available
memory
space, scrolling
up
or
down
is
possible
...
by line, page,
or
character.
®
MOTOROLA
Semiconductor
Products
Inc.
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