By using the CPU board block diagram, front panel indi-
1
cations and instrument operation troubleshooting time can
be reduced. An example problem is given to explain the pro-
cess involved.
Problem Observed:
Logic supply output offset by 80
mV
from the programmed voltage except when a voltage that
includes an 80
mV multiple is selected. Example:
Programmed Voltage Voltage Output
Step 1. Assumptions that can be made from this
information:
A. Power-up self-test passed, so CPU, ROM, RAM, ad-
dress and data bus are operational.
B.
From the nature of the problem, we can assume that
for some reason the data bit that controls the 80 mV
offset is stuck or the D-to-A converter is not respond-
ing correctly.
C. By checking the block diagram, we find that the logic
supply D-to-A converters data comes from the Serial
I10 section of the CPU board. This data is transferred
via a shift register on the logic supply board.
D.
We assume the instrument is calibrated correctly
since the output is correct when 80 mV multiples are
programmed.
Step 2: Procedure
Since checking signals on the logic supply board re-
quires extender boards, it may be a good idea to
check the data going from the Serial IIO section of the
CPU board. Use the Signature Analysis Mode,
Addressable Latch Test. If this shows an error, fix the
problem (verify that the output of the PS 5010 is cor-
rect). If outputs of latches are correct, then use Logic
Supply Shift Register Test. If the shift registers are all
right, then most likely the D-to-A converter is
defective.
REAR INTERFACE INFORMATION
Functions Available
at
Rear Connector
Slots exist between pins 19 and 20 and
6
and
7
on the
rear interface connectors. The slot between pins 19 and 20
is the family key slot. The slot between pins
6
and
7
identi-
fies the PS 5010 as a member of the TM 500-TM 5000
family. Insert a barrier in the corresponding position of the
power module jack to prevent noncompatible plug-ins from
being inserted in slots wired for the PS 5010. This protects
the plug-in if specialized connections are made to that com-
partment. Consult the power module manual for further in-
formation. Signal inputs, outputs and other specialized
I
WARNING
(
Maximum allowable voltage on any rear interface pin
is
42
V peak ac or
60
Vdc with respect to chassis
(earth) ground.
connections may be made to the rear interface connectors
Logic ~~~~l~ Scaled Current out (Logic Board
28A)
as shown in the inputloutput assignments illustrations (Figs.
6-6 and 6-7). The location and operation of the rear interface
This connector provides a voltage in relationship to the
switch is shown in Fig. 6-1. A description of these connec-
current supplied by the logic supply. See the specification
tions follows. GPlB connector assignments are shown in
section of this manual for the specified voltge. This output is
Fig. 6-8.
not ground referenced. Use pin 27A as the return.
REV
JAN
1983
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