FIRMWARE SIGNATURE ANALYSIS-ADDRESSABLE LATCHES
I.
Purpose
To troubleshoot the three addressable latches. Use this test to check the following ICs and their
functions.
A. Dim and relay latch-U1315
B.
Serial output and partial display latch-U1411
C. Blink control latch-U1314
II.
Equipment required
A. Tektronix SA 501 Signature Analyzer (or equivalent)
B.
Two TM 500 Flexible Extenders, Tektronix Part Number 067-0645-02
C. 16-pin DIP clip, Tektronix Part Number 003-0709-00 or equivalent
Ill.
Electrical conditions necessary to perform tests
A. CPU, RAM, ROM data, and address lines functional (verified by power-up self test).
B.
Startlstop test point (TP1401) functional. Check for pulses approximately 5.5 ms apart (low
true).
C. U1220, pin
6,
clock signal functional. Check for approximately a 1 MHz toggle.
IV.
Setup
A. PS 501 0 (on extenders)
1. Set GPlB address switch S1221 to ID 22.
Press
2. Set mode jumper (J132O) as shown.
Inputs Outputs
-
161514 13l2ll 10
9
Signature mode
,-
5-
.-
3-
7-
-,--s
Input/output
"
3
,?
.?
tz
,;,
F:
pinouts
f0r'U1310,
r'i'u=y=dd]
Ul3l4, Ul3l5
A
B
C
D
E
F
G
!!
0
.:.
..:..
.:..
.:..
.:..
.:..
....
and
Ul411
-:-
-,-,-.-.-.
3. Set runlforce data jumper (J1220) as shown.
m
12345678
w-
Inputs Outputs
1
Input
B.
Signature analyzer
Connect to CPU board and set as follows:
Threshold
=
TTL
Start
=
Connect to SIS test point (TP1401)
Stop
=
I
Connect to SIS test point (TPl4Ol)
Clock
=
I
Connect to U1220, pin 6 (via DIP clip)
CPU
board
Gnd
=
Connect to ground test point (TP1011)
V.
Measurements
Verify setup by taking +5 V and start signatures. Take measurements directly on U13l4, UW 5,
and U1411. If the chip enable signals are bad (pin 14), check U1310 (address decoder).
REV
AUG
1981
Fig.
9-5.
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