ME310G1 Hardware Design Guide
1VV0301588 Rev. 16 Page 44 of 95 2021-10-27
To avoid a back powering it is recommended to prevent any HIGH
logic level signals from being applied to the digital pins of the
ME310G1 when the module is powered off or during an ON/OFF
transition.
5.7.3.1 Asynchronous Serial Port (USIF1)
The serial port 1 on the Telit ME310G1 module is a +1.8V UART with 5 RS232 signals. It
differs from PC-RS232 in signal polarity (RS232 is reversed) and levels.
Warning: C104/RXD1 cannot have any PU or HIGH state during
BOOTING UP phase.
The following are the available signals:
Output transmit line of ME310G1
UART
Input receive of the
ME310G1 UART
Pull-up default during ON state
A3, A7, A9, A13, A17, B4,
B6, B10, B12, B14, B16,
C19, D18, F8, F12, F18,
G19, H6, H14, J19, K18,
M18, N19, P6, P14, T8,
T12, U1, V2, W19, Y2, Y4
Output from the ME310G1 that
controls the Hardware flow control
Input to the ME310G1 that controls
the Hardware flow control
Pull-up default during ON state
Table 30: ME310G1 port signals
5.7.3.2 Auxiliary Serial Port
The auxiliary serial port on the Telit ME310G1 module is a CMOS 1.8V with only the RX
and TX signals.
The following are the available serial port: