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SPRS717H –OCTOBER 2011–REVISED MAY 2015
Table 4-1. Pin Attributes (ZCE and ZCZ Packages) (continued)
BALL RESET BUFFER PULLUP
ZCE BALL ZCZ BALL TYPE BALL RESET RESET REL. ZCE POWER / HYS
PIN NAME [2] SIGNAL NAME [3] MODE [4] REL. STATE STRENGTH /DOWN TYPE I/O CELL [13]
NUMBER [1] NUMBER [1] [5] STATE [6] MODE [8] ZCZ POWER [9] [10]
[7] (mA) [11] [12]
NA V16 GPMC_A8 gpmc_a8 0 O L L 7 NA / VDDSHV3 Yes 6 PU/PD LVCMOS
gmii2_rxd3 1 I
rgmii2_rd3 2 I
mmc2_dat6 3 I/O
gpmc_a24 4 O
pr1_mii1_rxd0 5 I
mcasp0_aclkx 6 I/O
gpio1_24 7 I/O
NA U16 GPMC_A9
(10)
gpmc_a9 0 O L L 7 NA / VDDSHV3 Yes 6 PU/PD LVCMOS
gmii2_rxd2 1 I
rgmii2_rd2 2 I
mmc2_dat7 / rmii2_crs_dv 3 I/O
gpmc_a25 4 O
pr1_mii_mr1_clk 5 I
mcasp0_fsx 6 I/O
gpio1_25 7 I/O
NA T16 GPMC_A10 gpmc_a10 0 O L L 7 NA / VDDSHV3 Yes 6 PU/PD LVCMOS
gmii2_rxd1 1 I
rgmii2_rd1 2 I
rmii2_rxd1 3 I
gpmc_a26 4 O
pr1_mii1_rxdv 5 I
mcasp0_axr0 6 I/O
gpio1_26 7 I/O
NA V17 GPMC_A11 gpmc_a11 0 O L L 7 NA / VDDSHV3 Yes 6 PU/PD LVCMOS
gmii2_rxd0 1 I
rgmii2_rd0 2 I
rmii2_rxd0 3 I
gpmc_a27 4 O
pr1_mii1_rxer 5 I
mcasp0_axr1 6 I/O
gpio1_27 7 I/O
W10 U7 GPMC_AD0 gpmc_ad0 0 I/O L L 7 VDDSHV1 / Yes 6 PU/PD LVCMOS
VDDSHV1
mmc1_dat0 1 I/O
gpio1_0 7 I/O
V9 V7 GPMC_AD1 gpmc_ad1 0 I/O L L 7 VDDSHV1 / Yes 6 PU/PD LVCMOS
VDDSHV1
mmc1_dat1 1 I/O
gpio1_1 7 I/O
Copyright © 2011–2015, Texas Instruments Incorporated Terminal Configuration and Functions 25
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