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SPRS717H –OCTOBER 2011–REVISED MAY 2015
Table 4-1. Pin Attributes (ZCE and ZCZ Packages) (continued)
BALL RESET BUFFER PULLUP
ZCE BALL ZCZ BALL TYPE BALL RESET RESET REL. ZCE POWER / HYS
PIN NAME [2] SIGNAL NAME [3] MODE [4] REL. STATE STRENGTH /DOWN TYPE I/O CELL [13]
NUMBER [1] NUMBER [1] [5] STATE [6] MODE [8] ZCZ POWER [9] [10]
[7] (mA) [11] [12]
B7 B5 RTC_PWRONRSTn RTC_PORz 0 I Z Z 0 VDDS_RTC / Yes NA NA LVCMOS
VDDS_RTC
A6 A6 RTC_XTALIN OSC1_IN 0 I H H 0 VDDS_RTC / Yes NA PU
(1)
LVCMOS
VDDS_RTC
A5 A4 RTC_XTALOUT OSC1_OUT 0 O Z
(23)
Z
(23)
0 VDDS_RTC / NA NA
(15)
NA LVCMOS
VDDS_RTC
A18 A17 SPI0_SCLK spi0_sclk 0 I/O Z H 7 VDDSHV6 / Yes 6 PU/PD LVCMOS
VDDSHV6
uart2_rxd 1 I
I2C2_SDA 2 I/OD
ehrpwm0A 3 O
pr1_uart0_cts_n 4 I
pr1_edio_sof 5 O
EMU2 6 I/O
gpio0_2 7 I/O
A17 A16 SPI0_CS0 spi0_cs0 0 I/O Z H 7 VDDSHV6 / Yes 6 PU/PD LVCMOS
VDDSHV6
mmc2_sdwp 1 I
I2C1_SCL 2 I/OD
ehrpwm0_synci 3 I
pr1_uart0_txd 4 O
pr1_edio_data_in1 5 I
pr1_edio_data_out1 6 O
gpio0_5 7 I/O
B16 C15 SPI0_CS1 spi0_cs1 0 I/O Z H 7 VDDSHV6 / Yes 6 PU/PD LVCMOS
VDDSHV6
uart3_rxd 1 I
eCAP1_in_PWM1_out 2 I/O
mmc0_pow 3 O
xdma_event_intr2 4 I
mmc0_sdcd 5 I
EMU4 6 I/O
gpio0_6 7 I/O
B18 B17 SPI0_D0 spi0_d0 0 I/O Z H 7 VDDSHV6 / Yes 6 PU/PD LVCMOS
VDDSHV6
uart2_txd 1 O
I2C2_SCL 2 I/OD
ehrpwm0B 3 O
pr1_uart0_rts_n 4 O
pr1_edio_latch_in 5 I
EMU3 6 I/O
gpio0_3 7 I/O
Copyright © 2011–2015, Texas Instruments Incorporated Terminal Configuration and Functions 43
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