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SPRS717H –OCTOBER 2011–REVISED MAY 2015
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Table 4-1. Pin Attributes (ZCE and ZCZ Packages) (continued)
BALL RESET BUFFER PULLUP
ZCE BALL ZCZ BALL TYPE BALL RESET RESET REL. ZCE POWER / HYS
PIN NAME [2] SIGNAL NAME [3] MODE [4] REL. STATE STRENGTH /DOWN TYPE I/O CELL [13]
NUMBER [1] NUMBER [1] [5] STATE [6] MODE [8] ZCZ POWER [9] [10]
[7] (mA) [11] [12]
H17 G15 MMC0_DAT1 mmc0_dat1 0 I/O H H 7 VDDSHV4 / Yes 6 PU/PD LVCMOS
VDDSHV4
gpmc_a22 1 O
uart5_ctsn 2 I
uart3_rxd 3 I
uart1_dtrn 4 O
pr1_pru0_pru_r30_10 5 O
pr1_pru0_pru_r31_10 6 I
gpio2_28 7 I/O
H18 F18 MMC0_DAT2 mmc0_dat2 0 I/O H H 7 VDDSHV4 / Yes 6 PU/PD LVCMOS
VDDSHV4
gpmc_a21 1 O
uart4_rtsn 2 O
timer6 3 I/O
uart1_dsrn 4 I
pr1_pru0_pru_r30_9 5 O
pr1_pru0_pru_r31_9 6 I
gpio2_27 7 I/O
H19 F17 MMC0_DAT3 mmc0_dat3 0 I/O H H 7 VDDSHV4 / Yes 6 PU/PD LVCMOS
VDDSHV4
gpmc_a20 1 O
uart4_ctsn 2 I
timer5 3 I/O
uart1_dcdn 4 I
pr1_pru0_pru_r30_8 5 O
pr1_pru0_pru_r31_8 6 I
gpio2_26 7 I/O
C7 C6 PMIC_POWER_EN PMIC_POWER_EN 0 O H 1 0 VDDS_RTC / NA 6 NA LVCMOS
VDDS_RTC
E15 B15 PWRONRSTn porz 0 I Z Z 0 VDDSHV6 / Yes NA NA LVCMOS
VDDSHV6
(12)
B6 A3 RESERVED
(3)
testout 0 O NA NA NA VDDSHV6 / NA NA NA Analog
VDDSHV6
K18 H18 RMII1_REF_CLK rmii1_refclk 0 I/O L L 7 VDDSHV5 / Yes 6 PU/PD LVCMOS
VDDSHV5
xdma_event_intr2 1 I
spi1_cs0 2 I/O
uart5_txd 3 O
mcasp1_axr3 4 I/O
mmc0_pow 5 O
mcasp1_ahclkx 6 I/O
gpio0_29 7 I/O
A7 B4 RTC_KALDO_ENn ENZ_KALDO_1P8V 0 I Z Z 0 VDDS_RTC / NA NA NA Analog
VDDS_RTC
42 Terminal Configuration and Functions Copyright © 2011–2015, Texas Instruments Incorporated
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