Texas Instruments MSP430F5529 User Manual

MSP430F5529 , MSP430F5528 , MSP430F5527 , MSP430F5526
MSP430F5525 , MSP430F5524 , MSP430F5522 , MSP430F5521
MSP430F5519, MSP430F5517, MSP430F5515, MSP430F5514, MSP430F5513
SLAS590M –MARCH 2009–REVISED NOVEMBER 2015 www.ti.com
Table 4-1. Terminal Functions (continued)
TERMINAL
NO. I/O
(1)
DESCRIPTION
NAME
PN RGC YFF ZQE
General-purpose digital I/O
PJ.3/TCK
(4)
75 63 C2 B3 I/O
JTAG test clock
Reset input, active low
(5)
RST/NMI/SBWTDIO
(3)
76 64 D5 A2 I/O Nonmaskable interrupt input
Spy-Bi-Wire data input/output when Spy-Bi-Wire operation activated
General-purpose digital I/O
P6.0/CB0/A0 77 1 B1 A1 I/O Comparator_B input CB0
Analog input A0 – ADC (not available on F551x devices)
General-purpose digital I/O
P6.1/CB1/A1 78 2 C3 B2 I/O Comparator_B input CB1
Analog input A1 – ADC (not available on F551x devices)
General-purpose digital I/O
P6.2/CB2/A2 79 3 A1 B1 I/O Comparator_B input CB2
Analog input A2 – ADC (not available on F551x devices)
General-purpose digital I/O
P6.3/CB3/A3 80 4 C4 C2 I/O Comparator_B input CB3
Analog input A3 – ADC (not available on F551x devices)
Reserved N/A N/A N/A
(6)
Reserved. Connect to ground.
QFN Pad N/A Pad N/A N/A QFN package pad. TI recommends connecting to V
SS
.
(5) When this pin is configured as reset, the internal pullup resistor is enabled by default.
(6) C6, D4, D5, D6, E3, E4, E5, E6, F3, F4, F5, F6, F7, F8, G3 are reserved and should be connected to ground.
18 Terminal Configuration and Functions Copyright © 2009–2015, Texas Instruments Incorporated
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Product Folder Links: MSP430F5529 MSP430F5528 MSP430F5527 MSP430F5526 MSP430F5525 MSP430F5524
MSP430F5522 MSP430F5521 MSP430F5519 MSP430F5517 MSP430F5515 MSP430F5514 MSP430F5513

Texas Instruments MSP430F5529 Specifications

General

Brand	Texas Instruments
Model	MSP430F5529
Category	Microcontrollers
Language	English