Program Counter
PC/R0
Stack Pointer SP/R1
Status Register
SR/CG1/R2
Constant Generator CG2/R3
General-Purpose Register
R4
General-Purpose Register
R5
General-Purpose Register
R6
General-Purpose Register
R7
General-Purpose Register
R8
General-Purpose Register
R9
General-Purpose Register
R10
General-Purpose Register
R11
General-Purpose Register
R12
General-Purpose Register
R13
General-Purpose Register
R15
General-Purpose Register
R14
MSP430F5529
,
MSP430F5528
,
MSP430F5527
,
MSP430F5526
MSP430F5525
,
MSP430F5524
,
MSP430F5522
,
MSP430F5521
MSP430F5519, MSP430F5517, MSP430F5515, MSP430F5514, MSP430F5513
SLAS590M –MARCH 2009–REVISED NOVEMBER 2015
www.ti.com
6 Detailed Description
6.1 CPU (Link to User's Guide)
The MSP430 CPU has a 16-bit RISC architecture that is highly transparent to the application. All
operations, other than program-flow instructions, are performed as register operations in conjunction with
seven addressing modes for source operand and four addressing modes for destination operand.
The CPU is integrated with 16 registers that provide reduced instruction execution time. The register-to-
register operation execution time is one cycle of the CPU clock.
Four of the registers, R0 to R3, are dedicated as program counter, stack pointer, status register, and
constant generator, respectively. The remaining registers are general-purpose registers.
Peripherals are connected to the CPU using data, address, and control buses, and can be handled with all
instructions.
The instruction set consists of the original 51 instructions with three formats and seven address modes
and additional instructions for the expanded address range. Each instruction can operate on word and
byte data.
50 Detailed Description Copyright © 2009–2015, Texas Instruments Incorporated
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Product Folder Links: MSP430F5529 MSP430F5528 MSP430F5527 MSP430F5526 MSP430F5525 MSP430F5524
MSP430F5522 MSP430F5521 MSP430F5519 MSP430F5517 MSP430F5515 MSP430F5514 MSP430F5513
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