MSP430F5529
,
MSP430F5528
,
MSP430F5527
,
MSP430F5526
MSP430F5525
,
MSP430F5524
,
MSP430F5522
,
MSP430F5521
MSP430F5519, MSP430F5517, MSP430F5515, MSP430F5514, MSP430F5513
SLAS590M –MARCH 2009–REVISED NOVEMBER 2015
www.ti.com
5.7 Schmitt-Trigger Inputs – General-Purpose I/O
(1)
(P1.0 to P1.7, P2.0 to P2.7, P3.0 to P3.7, P4.0 to P4.7)
(P5.0 to P5.7, P6.0 to P6.7, P7.0 to P7.7, P8.0 to P8.2, PJ.0 to PJ.3, RST/NMI)
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER TEST CONDITIONS V
CC
MIN TYP MAX UNIT
1.8 V 0.80 1.40
V
IT+
Positive-going input threshold voltage V
3 V 1.50 2.10
1.8 V 0.45 1.00
V
IT–
Negative-going input threshold voltage V
3 V 0.75 1.65
1.8 V 0.3 0.85
V
hys
Input voltage hysteresis (V
IT+
– V
IT–
) V
3 V 0.4 1.0
For pullup: V
IN
= V
SS
R
Pull
Pullup and pulldown resistor
(2)
20 35 50 kΩ
For pulldown: V
IN
= V
CC
C
I
Input capacitance V
IN
= V
SS
or V
CC
5 pF
(1) Same parametrics apply to clock input pin when crystal bypass mode is used on XT1 (XIN) or XT2 (XT2IN).
(2) Also applies to RST pin when pullup or pulldown resistor is enabled.
5.8 Inputs – Ports P1 and P2
(1)
(P1.0 to P1.7, P2.0 to P2.7)
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER TEST CONDITIONS V
CC
MIN MAX UNIT
t
(int)
External interrupt timing
(2)
External trigger pulse duration to set interrupt flag 2.2 V, 3 V 20 ns
(1) Some devices may contain additional ports with interrupts. See the block diagram and terminal function descriptions.
(2) An external signal sets the interrupt flag every time the minimum interrupt pulse duration t
(int)
is met. It may be set by trigger signals
shorter than t
(int)
.
5.9 Leakage Current – General-Purpose I/O
(P1.0 to P1.7, P2.0 to P2.7, P3.0 to P3.7, P4.0 to P4.7)
(P5.0 to P5.7, P6.0 to P6.7, P7.0 to P7.7, P8.0 to P8.2, PJ.0 to PJ.3, RST/NMI)
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER TEST CONDITIONS V
CC
MIN MAX UNIT
I
lkg(Px.x)
High-impedance leakage current
(1) (2)
1.8 V, 3 V –50 50 nA
(1) The leakage current is measured with V
SS
or V
CC
applied to the corresponding pin(s), unless otherwise noted.
(2) The leakage of the digital port pins is measured individually. The port pin is selected for input and the pullup or pulldown resistor is
disabled.
5.10 Outputs – General-Purpose I/O (Full Drive Strength)
(P1.0 to P1.7, P2.0 to P2.7, P3.0 to P3.7, P4.0 to P4.7)
(P5.0 to P5.7, P6.0 to P6.7, P7.0 to P7.7, P8.0 to P8.2, PJ.0 to PJ.3)
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER TEST CONDITIONS V
CC
MIN MAX UNIT
I
(OHmax)
= –3 mA
(1)
V
CC
– 0.25 V
CC
1.8 V
I
(OHmax)
= –10 mA
(2)
V
CC
– 0.60 V
CC
V
OH
High-level output voltage V
I
(OHmax)
= –5 mA
(1)
V
CC
– 0.25 V
CC
3 V
I
(OHmax)
= –15 mA
(2)
V
CC
– 0.60 V
CC
I
(OLmax)
= 3 mA
(1)
V
SS
V
SS
+ 0.25
1.8 V
I
(OLmax)
= 10 mA
(2)
V
SS
V
SS
+ 0.60
V
OL
Low-level output voltage V
I
(OLmax)
= 5 mA
(1)
V
SS
V
SS
+ 0.25
3 V
I
(OLmax)
= 15 mA
(2)
V
SS
V
SS
+ 0.60
(1) The maximum total current, I
(OHmax)
and I
(OLmax)
, for all outputs combined should not exceed ±48 mA to hold the maximum voltage drop
specified.
(2) The maximum total current, I
(OHmax)
and I
(OLmax)
, for all outputs combined should not exceed ±100 mA to hold the maximum voltage
drop specified.
24 Specifications Copyright © 2009–2015, Texas Instruments Incorporated
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