MSP430F5529
,
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,
MSP430F5527
,
MSP430F5526
MSP430F5525
,
MSP430F5524
,
MSP430F5522
,
MSP430F5521
MSP430F5519, MSP430F5517, MSP430F5515, MSP430F5514, MSP430F5513
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SLAS590M –MARCH 2009–REVISED NOVEMBER 2015
5.33 USCI (SPI Slave Mode)
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
(1)
(see Figure 5-13 and Figure 5-14)
PARAMETER TEST CONDITIONS V
CC
MIN TYP MAX UNIT
1.8 V 11
PMMCOREV = 0
3.0 V 8
t
STE,LEAD
STE lead time, STE low to clock ns
2.4 V 7
PMMCOREV = 3
3.0 V 6
1.8 V 3
PMMCOREV = 0
3.0 V 3
t
STE,LAG
STE lag time, Last clock to STE high ns
2.4 V 3
PMMCOREV = 3
3.0 V 3
1.8 V 66
PMMCOREV = 0
3.0 V 50
STE access time, STE low to SOMI data
t
STE,ACC
ns
out
2.4 V 36
PMMCOREV = 3
3.0 V 30
1.8 V 30
PMMCOREV = 0
3.0 V 23
STE disable time, STE high to SOMI high
t
STE,DIS
ns
impedance
2.4 V 16
PMMCOREV = 3
3.0 V 13
1.8 V 5
PMMCOREV = 0
3.0 V 5
t
SU,SI
SIMO input data setup time ns
2.4 V 2
PMMCOREV = 3
3.0 V 2
1.8 V 5
PMMCOREV = 0
3.0 V 5
t
HD,SI
SIMO input data hold time ns
2.4 V 5
PMMCOREV = 3
3.0 V 5
1.8 V 76
UCLK edge to SOMI valid,
C
L
= 20 pF, PMMCOREV = 0
3.0 V 60
t
VALID,SO
SOMI output data valid time
(2)
ns
2.4 V 44
UCLK edge to SOMI valid,
C
L
= 20 pF, PMMCOREV = 3
3.0 V 40
1.8 V 18
C
L
= 20 pF, PMMCOREV = 0
3.0 V 12
t
HD,SO
SOMI output data hold time
(3)
ns
2.4 V 10
C
L
= 20 pF, PMMCOREV = 3
3.0 V 8
(1) f
UCxCLK
= 1/2t
LO/HI
with t
LO/HI
≥ max(t
VALID,MO(Master)
+ t
SU,SI(USCI)
, t
SU,MI(Master)
+ t
VALID,SO(USCI)
).
For the master parameters t
SU,MI(Master)
and t
VALID,MO(Master)
, see the SPI parameters of the attached slave.
(2) Specifies the time to drive the next valid data to the SOMI output after the output changing UCLK clock edge. See the timing diagrams
in Figure 5-13 and Figure 5-14.
(3) Specifies how long data on the SOMI output is valid after the output changing UCLK clock edge. See the timing diagrams in Figure 5-13
and Figure 5-14.
Copyright © 2009–2015, Texas Instruments Incorporated Specifications 37
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