1
2
3
RMII_MHz_50_CLK
RMII_TXEN
RMII_TXD[1:0]
RMII_RXD[1:0]
RMII_CRS_DV
RMII_RXER
6
7
11
9
8
5
4
10
5
RM46L852
SPNS185 –SEPTEMBER 2012
www.ti.com
5.12.2 Ethernet RMII Timing
Figure 5-24. RMII Timing Diagram
Table 5-38. RMII Timing Requirements
NO. Parameter Value Unit
MIN NOM MAX
1 tc(REFCLK) Cycle time, RMII_REF_CLK - 20 - ns
2 tw(REFCLKH) Pulse width, RMII_REF_CLK High 7 - 13 ns
3 tw(REFCLKL) Pulse width, RMII_REF_CLK Low 7 - 13 ns
6 tsu(RXD-REFCLK) Input setup time, RMII_RXD valid before 4 - - ns
RMII_REF_CLK High
7 th(REFCLK-RXD) Input hold time, RMII_RXD valid after 2 - - ns
RMII_REF_CLK High
8 tsu(CRSDV-REFCLK) Input setup time, RMII_CRSDV valid before 4 - - ns
RMII_REF_CLK High
9 th(REFCLK-CRSDV) Input hold time, RMII_CRSDV valid after 2 - - ns
RMII_REF_CLK High
10 tsu(RXER-REFCLK) Input setup time, RMII_RXER valid before 4 - - ns
RMII_REF_CLK High
11 th(REFCLK-RXER) Input hold time, RMII_RXER valid after 2 - - ns
RMII_REF_CLK High
4 td(REFCLK-TXD) Output delay time, RMII_REF_CLK High to 2 - 16 ns
RMII_TXD valid
5 td(REFCLK-TXEN) Output delay time, RMII_REF_CLK High to 2 - 16 ns
RMII_TX_EN valid
162 Peripheral Information and Electrical Specifications Copyright © 2012, Texas Instruments Incorporated
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