Texas Instruments RM46L852 User Manual

PRODUCTPREVIEW
HCLK (toSYSTEM)
GCLK,GCLK2 (toCPU)
GCM
VCLK_peri (VCLK to peripherals onPCR1)
VCLK2(toN2HETx andHTUx)
/1..16
/1..16
OSCIN
LowPower
Oscillator
10MHz
80kHz
PLL #1(FMzPLL)
1
0
4
5
/1..64
X1..256
/1..8
/1..32
6
PLL #2
*
/1,2,..256
SPIx,MibSPIx
/2,3..2
24
LIN,SCI
SPI
LIN /SCI
/1,2..32
MibADCx
ADCLK
/1,2..65536
ExternalClock
ECLK
VCLK2
N2HETx
HRP
/1..64
LRP
/2
0
..2
5
Loop
ResolutionClock
High
BaudRate
BaudRate
VCLK2
Ethernet
VCLKA4_DIVR
/1..64 X1..256 /1..8
/1..32 *
EXTCLKIN1
EXTCLKIN2
3
7
VCLKA1(to DCANx)to
0
1
4
5
6
VCLK
3
7
RTICLK (toRTI,DWWD)
/1,2,4,or8
VCLK
0
1
4
5
6
3
7
VCLK3
VCLK3(toEthernet,USB)
/1..16
VCLK_sys (VCLK to systemmodules)
*thefrequencyatthisnodemustnot
exceedthemaximumHCLKspecifiation.
/1,2..256
I2C
I2Cbaud
rate
0
1
4
5
6
VCLK
3
7
NTU[1]
NTU[0]
NTU[2]
NTU[3]
RTI
PLL#2output
EXTCLKIN1
Reserved
Reserved
VCLK
/1,2,..1024
Phase_seg2
CANBaudRate
Phase_seg1
VCLKA1
Prop_seg
(FMzPLL)
VCLKA3_S(leftopen)
/DIVR
VCLKA3_DIVR
(toUSBDevice/48MHZ
andUSBHost/48MHz)
USBHost
VCLKA3_DIVR/4
VCLKA3_DIVR
DCANx
EMIF USBDevice
VCLKA3_DIVR
N2HETx
TU
VCLKA4_DIVR
/DIVR
PLL2ODCLK/8
PLL2ODCLK/16
VCLKA4_DIVR_EMAC
(toEMAC)
VCLKA4_S(leftopen)
0
1
4
5
6
VCLK
3
7
/4
VCLKA3_DIVR/4
(toUSBHost/12MHz)
VCLKA4_SRC
RM46L852
SPNS185 –SEPTEMBER 2012 www.ti.com
4.6.2.2 Mapping of Clock Domains to Device Modules
Each clock domain has a dedicated functionality as shown in the figures below.
Figure 4-7. Device Clock Domains
68 System Information and Electrical Specifications Copyright © 2012, Texas Instruments Incorporated
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Texas Instruments RM46L852 Specifications

General

Brand	Texas Instruments
Model	RM46L852
Category	Microcontrollers
Language	English