RM46L852
SPNS185 –SEPTEMBER 2012
www.ti.com
Table 4-29. EMIF Asynchronous Memory Switching Characteristics
(1)(2)(3)
NO Parameter Value Unit
MIN NOM MAX
Reads and Writes
1 t
d(TURNAROUND)
Turn around time (TA)*E -3 (TA)*E (TA)*E + 3 ns
Reads
3 t
c(EMRCYCLE)
EMIF read cycle time (EW = 0) (RS+RST+RH)* (RS+RST+RH)* (RS+RST+RH)* ns
E -3 E E + 3
EMIF read cycle time (EW = 1) (RS+RST+RH+( (RS+RST+RH+( (RS+RST+RH+( ns
EWC*16))*E -3 EWC*16))*E EWC*16))*E +
3
4 t
su(EMCEL-EMOEL)
Output setup time, (RS)*E-3 (RS)*E (RS)*E+3 ns
EMIFnCS[4:2] low to EMIFnOE
low (SS = 0)
Output setup time, -3 0 +3 ns
EMIFnCS[4:2] low to EMIFnOE
low (SS = 1)
5 t
h(EMOEH-EMCEH)
Output hold time, EMIFnOE high (RH)*E -3 (RH)*E (RH)*E + 3 ns
to EMIFnCS[4:2] high (SS = 0)
Output hold time, EMIFnOE high -3 0 +3 ns
to EMIFnCS[4:2] high (SS = 1)
6 t
su(EMBAV-EMOEL)
Output setup time, EMIFBA[1:0] (RS)*E-3 (RS)*E (RS)*E+3 ns
valid to EMIFnOE low
7 t
h(EMOEH-EMBAIV)
Output hold time, EMIFnOE high (RH)*E-3 (RH)*E (RH)*E+3 ns
to EMIFBA[1:0] invalid
8 t
su(EMBAV-EMOEL)
Output setup time, (RS)*E-3 (RS)*E (RS)*E+3 ns
EMIFADDR[12:0] valid to
EMIFnOE low
9 t
h(EMOEH-EMAIV)
Output hold time, EMIFnOE high (RH)*E-3 (RH)*E (RH)*E+3 ns
to EMIFADDR[12:0] invalid
10 t
w(EMOEL)
EMIFnOE active low width (EW (RST)*E-3 (RST)*E (RST)*E+3 ns
= 0)
EMIFnOE active low width (EW (RST+(EWC*16 (RST+(EWC*16 (RST+(EWC*16 ns
= 1) )) *E-3 ))*E )) *E+3
11 t
d(EMWAITH-EMOEH)
Delay time from EMIFnWAIT 3E-3 4E 4E+3 ns
deasserted to EMIFnOE high
Writes
15 t
c(EMWCYCLE)
EMIF write cycle time (EW = 0) (WS+WST+WH (WS+WST+WH (WS+WST+WH ns
)* E-3 )*E )* E+3
EMIF write cycle time (EW = 1) (WS+WST+WH (WS+WST+WH (WS+WST+WH ns
+( EWC*16))*E +(E WC*16))*E +( EWC*16))*E
-3 + 3
16 t
su(EMCEL-EMWEL)
Output setup time, (WS)*E -3 (WS)*E (WS)*E + 3 ns
EMIFnCS[4:2] low to EMIFnWE
low (SS = 0)
Output setup time, -3 0 +3 ns
EMIFnCS[4:2] low to EMIFnWE
low (SS = 1)
17 t
h(EMWEH-EMCEH)
Output hold time, EMIFnWE (WH)*E-3 (WH)*E (WH)*E+3 ns
high to EMIFnCS[4:2] high (SS =
0)
(1) TA = Turn around, RS = Read setup, RST = Read strobe, RH = Read hold, WS = Write setup, WST = Write strobe, WH = Write hold,
MEWC = Maximum external wait cycles. These parameters are programmed via the Asynchronous Bank and Asynchronous Wait Cycle
Configuration Registers. These support the following ranges of values: TA[4–1], RS[16–1], RST[64–1], RH[8–1], WS[16–1], WST[64–1],
WH[8–1], and MEWC[1–256]. See the EMIF User’s guide for more information.
(2) E = EMIF_CLK period in ns.
(3) EWC = external wait cycles determined by EMIFnWAIT input signal. EWC supports the following range of values. EWC[256–1]. Note
that the maximum wait time before timeout is specified by bit field MEWC in the Asynchronous Wait Cycle Configuration Register. See
the EMIF User’s Guide for more information.
92 System Information and Electrical Specifications Copyright © 2012, Texas Instruments Incorporated
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