Texas Instruments TMS320C6748 - Page 128

A1
A1
DDR2/mDDRDevice
VREFNominalMinimum
TraceWidthis20Mils
VREFBypassCapacitor
NeckdowntominimuminBGA escape
regionsisacceptable.Narrowingto
accomodateviacongestionforshort
distancesisalsoacceptable.Best
performanceisobtainedifthewidth
ofVREFismaximized.
DDR2/mDDR
128
TMS320C6748
SPRS590G –JUNE 2009–REVISED JANUARY 2017 www.ti.com
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6.11.3.10 VREF Routing
VREF is used as a reference by the input buffers of the DDR2/mDDR memories as well as the C6748.
VREF is intended to be half the DDR2/mDDR power supply voltage and should be created using a
resistive divider as shown in Figure 6-18. Other methods of creating VREF are not recommended.
Figure 6-22 shows the layout guidelines for VREF.
Figure 6-22. VREF Routing and Topology