Texas Instruments TMS320C6748 User Manual

A1
A1
C B
A
T
DDR2/mDDR
Controller
129
TMS320C6748
www.ti.com SPRS590G –JUNE 2009–REVISED JANUARY 2017
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Peripheral Information and Electrical SpecificationsCopyright © 2009–2017, Texas Instruments Incorporated
(1) Center to center spacing is allowed to fall to minimum (w) for up to 500 mils of routed length to accommodate BGA escape and routing
congestion.
(2) w = PCB trace width as defined in Table 6-27.
(3) Series terminator, if used, should be located closest to device.
(4) CACLM is the longest Manhattan distance of the CK and ADDR_CTRL net classes.
6.11.3.11 DDR2/mDDR CK and ADDR_CTRL Routing
Figure 6-23 shows the topology of the routing for the CK and ADDR_CTRL net classes. The route is a
balanced T as it is intended that the length of segments B and C be equal. In addition, the length of A
should be maximized.
Figure 6-23. CK and ADDR_CTRL Routing and Topology
Table 6-34. CK and ADDR_CTRL Routing Specification
NO. PARAMETER MIN TYP MAX UNIT
1 Center to Center CK-CKN Spacing
(1)
2w
(2)
2 CK A to B/A to C Skew Length Mismatch
(3)
25 Mils
3 CK B to C Skew Length Mismatch 25 Mils
4 Center to center CK to other DDR2/mDDR trace spacing
(1)
4w
(2)
5 CK/ADDR_CTRL nominal trace length
(4)
CACLM-50 CACLM CACLM+50 Mils
6 ADDR_CTRL to CK Skew Length Mismatch 100 Mils
7 ADDR_CTRL to ADDR_CTRL Skew Length Mismatch 100 Mils
8 Center to center ADDR_CTRL to other DDR2/mDDR trace spacing
(1)
4w
(2)
9 Center to center ADDR_CTRL to other ADDR_CTRL trace spacing
(1)
3w
(2)
10 ADDR_CTRL A to B/A to C Skew Length Mismatch
(3)
100 Mils
11 ADDR_CTRL B to C Skew Length Mismatch 100 Mils

Texas Instruments TMS320C6748 Specifications

General

Brand	Texas Instruments
Model	TMS320C6748
Category	Control Unit
Language	English