Texas Instruments TMS320C6748 - Page 149

149
TMS320C6748
www.ti.com SPRS590G –JUNE 2009–REVISED JANUARY 2017
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Peripheral Information and Electrical SpecificationsCopyright © 2009–2017, Texas Instruments Incorporated
(1) McASP0 ACLKX0 internal – ACLKXCTL.CLKXM = 1, PDIR.ACLKX = 1
ACLKX0 external input – McASP0 ACLKXCTL.CLKXM = 0, PDIR.ACLKX = 0
ACLKX0 external output – McASP0ACLKXCTL.CLKXM = 0, PDIR.ACLKX = 1
ACLKR0 internal – McASP0 ACLKR0CTL.CLKRM = 1, PDIR.ACLKR =1
ACLKR0 external input – McASP0 ACLKRCTL.CLKRM = 0, PDIR.ACLKR = 0
ACLKR0 external output – McASP0 ACLKRCTL.CLKRM = 0, PDIR.ACLKR = 1
(2) AH = (AHCLKR/X period)/2 in ns. For example, when AHCLKR/X period is 25 ns, use AH = 12.5 ns.
(3) P = SYSCLK2 period
(4) This timing is limited by the timing shown or 2P, whichever is greater.
(5) A = (ACLKR/X period)/2 in ns. For example, when AHCLKR/X period is 25 ns, use AH = 12.5 ns.
(6) McASP0 ACLKXCTL.ASYNC=1: Receiver is clocked by its own ACLKR0
Table 6-54. Switching Characteristics for McASP0 (1.3V, 1.2V, 1.1V)
(1)
NO. PARAMETER
1.3V, 1.2V 1.1V
UNIT
MIN MAX MIN MAX
9 t
c(AHCLKRX)
Cycle time, AHCLKR/X 25 28 ns
10 t
w(AHCLKRX)
Pulse duration, AHCLKR/X high or low AH – 2.5
(2)
AH – 2.5
(2)
ns
11 t
c(ACLKRX)
Cycle time, ACLKR/X ACLKR/X int 25
(3)(4)
28
(3)(4)
ns
12 t
w(ACLKRX)
Pulse duration, ACLKR/X high or low ACLKR/X int A – 2.5
(5)
A – 2.5
(5)
ns
13 t
d(ACLKRX-AFSRX)
Delay time, ACLKR/X transmit edge
to AFSX/R output valid
(6)
ACLKR/X int -1 6 -1 8 ns
ACLKR/X ext input 2 13.5 2 14.5 ns
ACLKR/X ext output 2 13.5 2 14.5 ns
14 t
d(ACLKX-AXRV)
Delay time, ACLKX transmit edge to
AXR output valid
ACLKR/X int -1 6 -1 8 ns
ACLKR/X ext input 2 13.5 2 15 ns
ACLKR/X ext output 2 13.5 2 15 ns
15 t
dis(ACLKX-AXRHZ)
Disable time, ACLKR/X transmit
edge to AXR high impedance
following last data bit
ACLKR/X int 0 6 0 8 ns
ACLKR/X ext 2 13.5 2 15 ns
(1) McASP0 ACLKX0 internal – ACLKXCTL.CLKXM = 1, PDIR.ACLKX = 1
ACLKX0 external input – McASP0 ACLKXCTL.CLKXM = 0, PDIR.ACLKX = 0
ACLKX0 external output – McASP0ACLKXCTL.CLKXM = 0, PDIR.ACLKX = 1
ACLKR0 internal – McASP0 ACLKR0CTL.CLKRM = 1, PDIR.ACLKR =1
ACLKR0 external input – McASP0 ACLKRCTL.CLKRM = 0, PDIR.ACLKR = 0
ACLKR0 external output – McASP0 ACLKRCTL.CLKRM = 0, PDIR.ACLKR = 1
(2) AH = (AHCLKR/X period)/2 in ns. For example, when AHCLKR/X period is 25 ns, use AH = 12.5 ns.
(3) P = SYSCLK2 period
(4) This timing is limited by the timing shown or 2P, whichever is greater.
(5) A = (ACLKR/X period)/2 in ns. For example, when AHCLKR/X period is 25 ns, use AH = 12.5 ns.
(6) McASP0 ACLKXCTL.ASYNC=1: Receiver is clocked by its own ACLKR0
Table 6-55. Switching Characteristics for McASP0 (1.0V)
(1)
NO. PARAMETER
1.0V
UNIT
MIN MAX
9 t
c(AHCLKRX)
Cycle time, AHCLKR/X 35 ns
10 t
w(AHCLKRX)
Pulse duration, AHCLKR/X high or low AH – 2.5
(2)
ns
11 t
c(ACLKRX)
Cycle time, ACLKR/X ACLKR/X int 35
(3)(4)
ns
12 t
w(ACLKRX)
Pulse duration, ACLKR/X high or low ACLKR/X int A – 2.5
(5)
ns
13 t
d(ACLKRX-AFSRX)
Delay time, ACLKR/X transmit edge to AFSX/R output
valid
(6)
ACLKR/X int -0.5 10 ns
ACLKR/X ext input 2 19 ns
ACLKR/X ext output 2 19 ns
14 t
d(ACLKX-AXRV)
Delay time, ACLKX transmit edge to AXR output valid
ACLKR/X int -0.5 10 ns
ACLKR/X ext input 2 19 ns
ACLKR/X ext output 2 19 ns
15 t
dis(ACLKX-AXRHZ)
Disable time, ACLKR/X transmit edge to AXR high
impedance following last data bit
ACLKR/X int 0 10 ns
ACLKR/X ext 2 19 ns