Texas Instruments TMS320C6748 - Page 173

173
TMS320C6748
www.ti.com SPRS590G –JUNE 2009–REVISED JANUARY 2017
Submit Documentation Feedback
Product Folder Links: TMS320C6748
Peripheral Information and Electrical SpecificationsCopyright © 2009–2017, Texas Instruments Incorporated
(1) These parameters are in addition to the general timings for SPI master modes (Table 6-76).
(2) P = SYSCLK2 period; M = t
c(SPC)M
(SPI master bit clock period)
(3) Figure shows only Polarity = 0, Phase = 0 as an example. Table gives parameters for all four master clocking modes.
(4) In the case where the master SPI is ready with new data before SPI1_ENA assertion.
(5) In the case where the master SPI is ready with new data before SPI1_ENA deassertion.
Table 6-78. Additional
(1)
SPI1 Master Timings, 4-Pin Enable Option
(2)(3)
NO. PARAMETER
1.3V, 1.2V 1.1V 1.0V
UNIT
MIN MAX MIN MAX MIN MAX
17 t
d(EN A_SPC)M
Delay from slave
assertion of
SPI1_ENA active to
first SPI1_CLK from
master.
(4)
Polarity = 0, Phase = 0,
to SPI1_CLK rising
3P+5 3P+5 3P+6
ns
Polarity = 0, Phase = 1,
to SPI1_CLK rising
0.5M+3P+5 0.5M+3P+5 0.5M+3P+6
Polarity = 1, Phase = 0,
to SPI1_CLK falling
3P+5 3P+5 3P+6
Polarity = 1, Phase = 1,
to SPI1_CLK falling
0.5M+3P+5 0.5M+3P+5 0.5M+3P+6
18 t
d(SPC_ENA)M
Max delay for slave to
deassert SPI1_ENA
after final SPI1_CLK
edge to ensure
master does not begin
the next transfer.
(5)
Polarity = 0, Phase = 0,
from SPI1_CLK falling
0.5M+P+5 0.5M+P+5 0.5M+P+6
ns
Polarity = 0, Phase = 1,
from SPI1_CLK falling
P+5 P+5 P+6
Polarity = 1, Phase = 0,
from SPI1_CLK rising
0.5M+P+5 0.5M+P+5 0.5M+P+6
Polarity = 1, Phase = 1,
from SPI1_CLK rising
P+5 P+5 P+6
(1) These parameters are in addition to the general timings for SPI master modes (Table 6-76).
(2) P = SYSCLK2 period; M = t
c(SPC)M
(SPI master bit clock period)
(3) Figure shows only Polarity = 0, Phase = 0 as an example. Table gives parameters for all four master clocking modes.
(4) In the case where the master SPI is ready with new data before SPI1_SCS assertion.
(5) This delay can be increased under software control by the register bit field SPIDELAY.C2TDELAY[4:0].
(6) Except for modes when SPIDAT1.CSHOLD is enabled and there is additional data to transmit. In this case, SPI1_SCS will remain
asserted.
(7) This delay can be increased under software control by the register bit field SPIDELAY.T2CDELAY[4:0].
Table 6-79. Additional
(1)
SPI1 Master Timings, 4-Pin Chip Select Option
(2) (3)
NO. PARAMETER
1.3V, 1.2V 1.1V 1.0V
UNIT
MIN MAX MIN MAX MIN MAX
19 t
d(SCS_SPC)M
Delay from
SPI1_SCS active
to first
SPI1_CLK
(4) (5)
Polarity = 0, Phase = 0,
to SPI1_CLK rising
2P-1 2P-5 2P-6
ns
Polarity = 0, Phase = 1,
to SPI1_CLK rising
0.5M+2P-1 0.5M+2P-5 0.5M+2P-6
Polarity = 1, Phase = 0,
to SPI1_CLK falling
2P-1 2P-5 2P-6
Polarity = 1, Phase = 1,
to SPI1_CLK falling
0.5M+2P-1 0.5M+2P-5 0.5M+2P-6
20 t
d(SPC_SCS)M
Delay from final
SPI1_CLK edge to
master
deasserting
SPI1_SCS
(6) (7)
Polarity = 0, Phase = 0,
from SPI1_CLK falling
0.5M+P-1 0.5M+P-5 0.5M+P-6
ns
Polarity = 0, Phase = 1,
from SPI1_CLK falling
P-1 P-5 P-6
Polarity = 1, Phase = 0,
from SPI1_CLK rising
0.5M+P-1 0.5M+P-5 0.5M+P-6
Polarity = 1, Phase = 1,
from SPI1_CLK rising
P-1 P-5 P-6