Texas Instruments TMS320C6748 - Page 172

172
TMS320C6748
SPRS590G –JUNE 2009–REVISED JANUARY 2017 www.ti.com
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Peripheral Information and Electrical Specifications Copyright © 2009–2017, Texas Instruments Incorporated
(1) P = SYSCLK2 period; S = t
c(SPC)S
(SPI slave bit clock period)
(2) This timing is limited by the timing shown or 3P, whichever is greater.
(3) First bit may be MSB or LSB depending upon SPI configuration. SO(0) refers to first bit and SO(n) refers to last bit output on
SPI1_SOMI. SI(0) refers to the first bit input and SI(n) refers to the last bit input on SPI1_SIMO.
(4) Measured from the termination of the write of new data to the SPI module, In analyzing throughput requirements, additional internal bus
cycles must be accounted for to allow data to be written to the SPI module by the CPU.
Table 6-77. General Timing Requirements for SPI1 Slave Modes
(1)
NO.
1.3V, 1.2V 1.1V 1.0V
UNIT
MIN MAX MIN MAX MIN MAX
9 t
c(SPC)S
Cycle Time, SPI1_CLK, All Slave Modes 40
(2)
50
(2)
60
(2)
ns
10 t
w(SPCH)S
Pulse Width High, SPI1_CLK, All Slave Modes 18 22 27 ns
11 t
w(SPCL)S
Pulse Width Low, SPI1_CLK, All Slave Modes 18 22 27 ns
12 t
su(SOMI_SPC)S
Setup time, transmit data
written to SPI before initial
clock edge from
master.
(3)(4)
Polarity = 0, Phase = 0,
to SPI1_CLK rising
2P 2P 2P
ns
Polarity = 0, Phase = 1,
to SPI1_CLK rising
2P 2P 2P
Polarity = 1, Phase = 0,
to SPI1_CLK falling
2P 2P 2P
Polarity = 1, Phase = 1,
to SPI1_CLK falling
2P 2P 2P
13 t
d(SPC_SOMI)S
Delay, subsequent bits valid
on SPI1_SOMI after transmit
edge of SPI1_CLK
Polarity = 0, Phase = 0,
from SPI1_CLK rising
15 17 19
ns
Polarity = 0, Phase = 1,
from SPI1_CLK falling
15 17 19
Polarity = 1, Phase = 0,
from SPI1_CLK falling
15 17 19
Polarity = 1, Phase = 1,
from SPI1_CLK rising
15 17 19
14 t
oh(SPC_SOMI)S
Output hold time, SPI1_SOMI
valid after receive edge of
SPI1_CLK
Polarity = 0, Phase = 0,
from SPI1_CLK falling
0.5S-4 0.5S-10 0.5S-12
ns
Polarity = 0, Phase = 1,
from SPI1_CLK rising
0.5S-4 0.5S-10 0.5S-12
Polarity = 1, Phase = 0,
from SPI1_CLK rising
0.5S-4 0.5S-10 0.5S-12
Polarity = 1, Phase = 1,
from SPI1_CLK falling
0.5S-4 0.5S-10 0.5S-12
15 t
su(SIMO_SPC)S
Input Setup Time, SPI1_SIMO
valid before receive edge of
SPI1_CLK
Polarity = 0, Phase = 0,
to SPI1_CLK falling
1.5 1.5 1.5
ns
Polarity = 0, Phase = 1,
to SPI1_CLK rising
1.5 1.5 1.5
Polarity = 1, Phase = 0,
to SPI1_CLK rising
1.5 1.5 1.5
Polarity = 1, Phase = 1,
to SPI1_CLK falling
1.5 1.5 1.5
16 t
ih(SPC_SIMO)S
Input Hold Time, SPI1_SIMO
valid after receive edge of
SPI1_CLK
Polarity = 0, Phase = 0,
from SPI1_CLK falling
4 5 6
ns
Polarity = 0, Phase = 1,
from SPI1_CLK rising
4 5 6
Polarity = 1, Phase = 0,
from SPI1_CLK rising
4 5 6
Polarity = 1, Phase = 1,
from SPI1_CLK falling
4 5 6