Texas Instruments TMS320C6748 - Page 171

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TMS320C6748
www.ti.com SPRS590G –JUNE 2009–REVISED JANUARY 2017
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Peripheral Information and Electrical SpecificationsCopyright © 2009–2017, Texas Instruments Incorporated
(1) P = SYSCLK2 period; M = t
c(SPC)M
(SPI master bit clock period)
(2) This timing is limited by the timing shown or 3P, whichever is greater.
(3) First bit may be MSB or LSB depending upon SPI configuration. MO(0) refers to first bit and MO(n) refers to last bit output on
SPI1_SIMO. MI(0) refers to the first bit input and MI(n) refers to the last bit input on SPI1_SOMI.
Table 6-76. General Timing Requirements for SPI1 Master Modes
(1)
NO.
1.3V, 1.2V 1.1V 1.0V
UNIT
MIN MAX MIN MAX MIN MAX
1 t
c(SPC)M
Cycle Time, SPI1_CLK, All Master Modes 20
(2)
256P 30
(2)
256P 40
(2)
256P ns
2 t
w(SPCH)M
Pulse Width High, SPI1_CLK, All Master Modes 0.5M-1 0.5M-1 0.5M-1 ns
3 t
w(SPCL)M
Pulse Width Low, SPI1_CLK, All Master Modes 0.5M-1 0.5M-1 0.5M-1 ns
4 t
d(SIMO_SPC)M
Delay, initial data bit valid on
SPI1_SIMO to initial edge on
SPI1_CLK
(3)
Polarity = 0, Phase = 0,
to SPI1_CLK rising
5 5 6
ns
Polarity = 0, Phase = 1,
to SPI1_CLK rising
-0.5M+5 -0.5M+5 -0.5M+6
Polarity = 1, Phase = 0,
to SPI1_CLK falling
5 5 6
Polarity = 1, Phase = 1,
to SPI1_CLK falling
-0.5M+5 -0.5M+5 -0.5M+6
5 t
d(SPC_SIMO)M
Delay, subsequent bits valid on
SPI1_SIMO after transmit edge
of SPI1_CLK
Polarity = 0, Phase = 0,
from SPI1_CLK rising
5 5 6
ns
Polarity = 0, Phase = 1,
from SPI1_CLK falling
5 5 6
Polarity = 1, Phase = 0,
from SPI1_CLK falling
5 5 6
Polarity = 1, Phase = 1,
from SPI1_CLK rising
5 5 6
6 t
oh(SPC_SIMO)M
Output hold time, SPI1_SIMO
valid after receive edge of
SPI1_CLK
Polarity = 0, Phase = 0,
from SPI1_CLK falling
0.5M-3 0.5M-3 0.5M-3
ns
Polarity = 0, Phase = 1,
from SPI1_CLK rising
0.5M-3 0.5M-3 0.5M-3
Polarity = 1, Phase = 0,
from SPI1_CLK rising
0.5M-3 0.5M-3 0.5M-3
Polarity = 1, Phase = 1,
from SPI1_CLK falling
0.5M-3 0.5M-3 0.5M-3
7 t
su(SOMI_SPC)M
Input Setup Time, SPI1_SOMI
valid before receive edge of
SPI1_CLK
Polarity = 0, Phase = 0,
to SPI1_CLK falling
1.5 1.5 1.5
ns
Polarity = 0, Phase = 1,
to SPI1_CLK rising
1.5 1.5 1.5
Polarity = 1, Phase = 0,
to SPI1_CLK rising
1.5 1.5 1.5
Polarity = 1, Phase = 1,
to SPI1_CLK falling
1.5 1.5 1.5
8 t
ih(SPC_SOMI)M
Input Hold Time, SPI1_SOMI
valid after receive edge of
SPI1_CLK
Polarity = 0, Phase = 0,
from SPI1_CLK falling
4 5 6
ns
Polarity = 0, Phase = 1,
from SPI1_CLK rising
4 5 6
Polarity = 1, Phase = 0,
from SPI1_CLK rising
4 5 6
Polarity = 1, Phase = 1,
from SPI1_CLK falling
4 5 6