Texas Instruments TMS320C6748 - Page 170

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TMS320C6748
SPRS590G –JUNE 2009–REVISED JANUARY 2017 www.ti.com
Table 6-75. Additional SPI0 Slave Timings, 5-Pin Option
(1)(2)(3)
(continued)
NO. PARAMETER
1.3V, 1.2V 1.1V 1.0V
UNIT
MIN MAX MIN MAX MIN MAX
(4) SPI0_ENA is driven low after the transmission completes if the SPIINT0.ENABLE_HIGHZ bit is programmed to 0. Otherwise it is tri-stated. If tri-stated, an external pullup resistor should
be used to provide a valid level to the master. This option is useful when tying several SPI slave devices to a single master.
30 t
dis(SPC_ENA)S
Delay from final clock receive
edge on SPI0_CLK to slave 3-
stating or driving high
SPI0_ENA.
(4)
Polarity = 0, Phase = 0,
from SPI0_CLK falling
2.5P+17.5 2.5P+20 2.5P+27
ns
Polarity = 0, Phase = 1,
from SPI0_CLK rising
2.5P+17.5 2.5P+20 2.5P+27
Polarity = 1, Phase = 0,
from SPI0_CLK rising
2.5P+17.5 2.5P+20 2.5P+27
Polarity = 1, Phase = 1,
from SPI0_CLK falling
2.5P+17.5 2.5P+20 2.5P+27