Texas Instruments TMS320C6748 User Manual

Copyright © 2009–2017, Texas Instruments Incorporated Peripheral Information and Electrical Specifications
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TMS320C6748
www.ti.com SPRS590G –JUNE 2009–REVISED JANUARY 2017
(1) These parameters are in addition to the general timings for SPI slave modes (Table 6-69).
(2) P = SYSCLK2 period; M = t
c(SPC)M
(SPI master bit clock period)
(3) Figure shows only Polarity = 0, Phase = 0 as an example. Table gives parameters for all four slave clocking modes.
Table 6-74. Additional SPI0 Slave Timings, 4-Pin Chip Select Option
(1)(2)(3)
NO. PARAMETER
1.3V, 1.2V 1.1V 1.0V
UNIT
MIN MAX MIN MAX MIN MAX
25 t
d(SCSL_SPC)S
Required delay from SPI0_SCS asserted at slave to first SPI0_CLK edge
at slave.
P + 1.5 P + 1.5 P + 1.5 ns
26 t
d(SPC_SCSH)S
Required delay from final SPI0_CLK edge
before SPI0_SCS is deasserted.
Polarity = 0, Phase = 0,
from SPI0_CLK falling
0.5M+P+4 0.5M+P+4 0.5M+P+5
ns
Polarity = 0, Phase = 1,
from SPI0_CLK falling
P+4 P+4 P+5
Polarity = 1, Phase = 0,
from SPI0_CLK rising
0.5M+P+4 0.5M+P+4 0.5M+P+5
Polarity = 1, Phase = 1,
from SPI0_CLK rising
P+4 P+4 P+5
27 t
ena(SCSL_SOMI)S
Delay from master asserting SPI0_SCS to slave driving SPI0_SOMI valid P+17.5 P+20 P+27 ns
28 t
dis(SCSH_SOMI)S
Delay from master deasserting SPI0_SCS to slave 3-stating SPI0_SOMI P+17.5 P+20 P+27 ns
(1) These parameters are in addition to the general timings for SPI slave modes (Table 6-69).
(2) P = SYSCLK2 period; M = t
c(SPC)M
(SPI master bit clock period)
(3) Figure shows only Polarity = 0, Phase = 0 as an example. Table gives parameters for all four slave clocking modes.
Table 6-75. Additional SPI0 Slave Timings, 5-Pin Option
(1)(2)(3)
NO. PARAMETER
1.3V, 1.2V 1.1V 1.0V
UNIT
MIN MAX MIN MAX MIN MAX
25 t
d(SCSL_SPC)S
Required delay from SPI0_SCS asserted at slave to first
SPI0_CLK edge at slave.
P + 1.5 P + 1.5 P + 1.5 ns
26 t
d(SPC_SCSH)S
Required delay from final
SPI0_CLK edge before SPI0_SCS
is deasserted.
Polarity = 0, Phase = 0,
from SPI0_CLK falling
0.5M+P+4 0.5M+P+4 0.5M+P+5
ns
Polarity = 0, Phase = 1,
from SPI0_CLK falling
P+4 P+4 P+5
Polarity = 1, Phase = 0,
from SPI0_CLK rising
0.5M+P+4 0.5M+P+4 0.5M+P+5
Polarity = 1, Phase = 1,
from SPI0_CLK rising
P+4 P+4 P+5
27 t
ena(SCSL_SOMI)S
Delay from master asserting SPI0_SCS to slave driving
SPI0_SOMI valid
P+17.5 P+20 P+27 ns
28 t
dis(SCSH_SOMI)S
Delay from master deasserting SPI0_SCS to slave 3-stating
SPI0_SOMI
P+17.5 P+20 P+27 ns
29 t
ena(SCSL_ENA)S
Delay from master deasserting SPI0_SCS to slave driving
SPI0_ENA valid
17.5 20 27 ns

Texas Instruments TMS320C6748 Specifications

General

Brand	Texas Instruments
Model	TMS320C6748
Category	Control Unit
Language	English

Summary

Device Overview

Features

Lists the key features of the TMS320C674x Fixed- and Floating-Point VLIW DSP.

Description

Functional Block Diagram

Device Comparison

Device Characteristics

Overview of C6748 hardware features, peripherals, on-chip memory, and package type.

Memory Map Summary

Pin Assignments

Pin Multiplexing Control

Terminal Functions

Device Reset, NMI and JTAG Terminal Functions

Details terminal functions for RESET, NMI, and JTAG signals.

External Memory Interface A (EMIFA) Terminal Functions

Details terminal functions for the External Memory Interface A.

DDR2/mDDR Controller Terminal Functions

Details terminal functions for the DDR2/mDDR Memory Controller.

Serial Peripheral Interface Modules (SPI) Terminal Functions

Details terminal functions for SPI0 and SPI1 modules.

Programmable Real-Time Unit (PRU) Terminal Functions

Details terminal functions for the Programmable Real-Time Unit.

Boot

Details boot mode selection terminal functions.

Universal Asynchronous Receiver/Transmitters (UART0, UART1, UART2) Terminal Functions

Details terminal functions for UART0, UART1, and UART2.

Inter-Integrated Circuit Modules(I2C0, I2C1) Terminal Functions

Details terminal functions for I2C0 and I2C1 modules.

Multichannel Audio Serial Ports (McASP) Terminal Functions

Details terminal functions for McASP modules.

Multichannel Buffered Serial Ports (McBSP) Terminal Functions

Details terminal functions for McBSP modules.

Universal Serial Bus Modules (USB0, USB1) Terminal Functions

Details terminal functions for USB0 and USB1 modules.

Ethernet Media Access Controller (EMAC) Terminal Functions

Details terminal functions for the EMAC module.

Multimedia Card/Secure Digital (MMC/SD) Terminal Functions

Details terminal functions for MMC/SD card interfaces.

Liquid Crystal Display Controller(LCD) Terminal Functions

Details terminal functions for the LCD controller.

Serial ATA Controller (SATA) Terminal Functions

Details terminal functions for the SATA controller.

Universal Host-Port Interface (UHPI) Terminal Functions

Details terminal functions for the UHPI interface.

Universal Parallel Port (uPP) Terminal Functions

Details terminal functions for the Universal Parallel Port.

Video Port Interface (VPIF) Terminal Functions

Details terminal functions for the Video Port Interface.

Supply and Ground Terminal Functions

Details terminal functions for supply and ground pins.

Device Configuration

Boot Modes

Describes the various boot modes supported by the internal DSP ROM bootloader.

Pullup/Pulldown Resistors

Specifications

Absolute Maximum Ratings Over Operating Junction Temperature Range

Specifies the absolute maximum ratings for voltage and temperature.

Handling Ratings

Details handling precautions, including ESD voltage ratings.

Recommended Operating Conditions

Specifies recommended operating conditions for supply voltage and junction temperature.

Electrical Characteristics Over Recommended Ranges of Supply Voltage and Operating Junction Temperature

Details electrical characteristics over recommended operating ranges.

Power Supplies

Power-On Sequence

Describes the required order for powering on the device's various supplies.

Reset

Power-On Reset (POR)

Explains the Power-On Reset behavior and its effects on device logic and pins.

Reset Electrical Data Timings

Crystal Oscillator or External Clock Input

Clock PLLs

Enhanced Direct Memory Access Controller (EDMA3)

EDMA3 Peripheral Register Descriptions

Describes the EDMA3 Channel Controller and Transfer Controller registers.

Interrupts

DSP Interrupts

Details the C674x DSP interrupt controller, prioritized interrupts, and registers.

Power and Sleep Controller (PSC)

Memory Protection Units

MPU1 Configuration Registers

MPU2 Configuration Registers

MMC / SD / SDIO (MMCSD0, MMCSD1)

MMCSD Peripheral Register Description(s)

MMC/SD Electrical Data/Timing

Serial ATA Controller (SATA)

SATA Register Descriptions

Multichannel Audio Serial Port (McASP)

McASP Peripheral Registers Description(s)

McASP Electrical Data/Timing

Multichannel Buffered Serial Port (McBSP)

McBSP Peripheral Register Description(s)

McBSP Electrical Data/Timing

Serial Peripheral Interface Ports (SPI0, SPI1)

SPI Peripheral Registers Description(s)

SPI Electrical Data/Timing

Inter-Integrated Circuit Serial Ports (I2C)

I2C Peripheral Registers Description(s)

Universal Asynchronous Receiver/Transmitter (UART)

UART Peripheral Registers Description(s)

UART Electrical Data/Timing

Universal Serial Bus OTG Controller (USB0) [USB2.0 OTG]

Universal Serial Bus OTG (USB0) Registers

USB0 [USB2.0] Electrical Data/Timing

Universal Serial Bus Host Controller (USB1) [USB1.1 OHCI]

USB Host Controller Registers

Ethernet Media Access Controller (EMAC)

EMAC Peripheral Register Description(s)

EMAC Electrical Data/Timing

LCD Controller (LCDC)

LCD Controller Registers

Host-Port Interface (UHPI)

HPI Peripheral Register Description(s)

HPI Electrical Data/Timing

Universal Parallel Port (uPP)

uPP Register Descriptions

uPP Electrical Data/Timing

Video Port Interface (VPIF)

VPIF Register Descriptions

VPIF Electrical Data/Timing

Enhanced Capture (eCAP) Peripheral

ECAPx Configuration Registers

Enhanced Pulse Width Modulator (eHRPWM) Timing

Real Time Clock (RTC)

Real-Time Clock Register Descriptions

General-Purpose Input/Output (GPIO)

GPIO Register Description(s)

Programmable Real-Time Unit Subsystem (PRUSS)

PRUSS Register Descriptions

Emulation Logic

JTAG Port Description

Electrostatic Discharge Caution