Texas Instruments TMS320C6748 - Page 175

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TMS320C6748
www.ti.com SPRS590G –JUNE 2009–REVISED JANUARY 2017
Table 6-80. Additional
(1)
SPI1 Master Timings, 5-Pin Option
(2)(3)
(continued)
NO. PARAMETER
1.3V, 1.2V 1.1V 1.0V
UNIT
MIN MAX MIN MAX MIN MAX
(10) If SPI1_ENA was initially deasserted high and SPI1_CLK is delayed.
23 t
d(ENA_SPC)M
Delay from assertion of SPI1_ENA
low to first SPI1_CLK edge.
(10)
Polarity = 0, Phase = 0,
to SPI1_CLK rising
3P+5 3P+5 3P+6
ns
Polarity = 0, Phase = 1,
to SPI1_CLK rising
0.5M+3P+5 0.5M+3P+5 0.5M+3P+6
Polarity = 1, Phase = 0,
to SPI1_CLK falling
3P+5 3P+5 3P+6
Polarity = 1, Phase = 1,
to SPI1_CLK falling
0.5M+3P+5 0.5M+3P+5 0.5M+3P+6
(1) These parameters are in addition to the general timings for SPI slave modes (Table 6-77).
(2) P = SYSCLK2 period; M = t
c(SPC)M
(SPI master bit clock period)
(3) Figure shows only Polarity = 0, Phase = 0 as an example. Table gives parameters for all four slave clocking modes.
Table 6-81. Additional
(1)
SPI1 Slave Timings, 4-Pin Enable Option
(2)(3)
NO. PARAMETER
1.3V, 1.2V 1.1V 1.0V
UNIT
MIN MAX MIN MAX MIN MAX
24 t
d(SPC_ENAH)S
Delay from final SPI1_CLK edge to
slave deasserting SPI1_ENA.
Polarity = 0, Phase = 0,
from SPI1_CLK falling
1.5P-3 2.5P+15 1.5P-10 2.5P+17 1.5P-12 2.5P+19
ns
Polarity = 0, Phase = 1,
from SPI1_CLK falling
–0.5M+1.5P-3 –0.5M+2.5P+15 –0.5M+1.5P-10 –0.5M+2.5P+17 –0.5M+1.5P-12 –0.5M+2.5P+19
Polarity = 1, Phase = 0,
from SPI1_CLK rising
1.5P-3 2.5P+15 1.5P-10 2.5P+17 1.5P-12 2.5P+19
Polarity = 1, Phase = 1,
from SPI1_CLK rising
–0.5M+1.5P-3 –0.5M+2.5P+15 –0.5M+1.5P-10 –0.5M+2.5P+17 –0.5M+1.5P-12 –0.5M+2.5P+19