Texas Instruments TMS320C6748 - Page 176

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TMS320C6748
SPRS590G –JUNE 2009–REVISED JANUARY 2017 www.ti.com
(1) These parameters are in addition to the general timings for SPI slave modes (Table 6-77).
(2) P = SYSCLK2 period; M = t
c(SPC)M
(SPI master bit clock period)
(3) Figure shows only Polarity = 0, Phase = 0 as an example. Table gives parameters for all four slave clocking modes.
Table 6-82. Additional
(1)
SPI1 Slave Timings, 4-Pin Chip Select Option
(2)(3)
NO. PARAMETER
1.3V, 1.2V 1.1V 1.0V
UNIT
MIN MAX MIN MAX MIN MAX
25 t
d(SCSL_SPC)S
Required delay from SPI1_SCS asserted at slave to first SPI1_CLK edge at
slave.
P+1.5 P+1.5 P+1.5 ns
26 t
d(SPC_SCSH)S
Required delay from final SPI1_CLK edge
before SPI1_SCS is deasserted.
Polarity = 0, Phase = 0,
from SPI1_CLK falling
0.5M+P+4 0.5M+P+5 0.5M+P+6
ns
Polarity = 0, Phase = 1,
from SPI1_CLK falling
P+4 P+5 P+6
Polarity = 1, Phase = 0,
from SPI1_CLK rising
0.5M+P+4 0.5M+P+5 0.5M+P+6
Polarity = 1, Phase = 1,
from SPI1_CLK rising
P+4 P+5 P+6
27 t
ena(SCSL_SOMI)S
Delay from master asserting SPI1_SCS to slave driving SPI1_SOMI valid P+15 P+17 P+19 ns
28 t
dis(SCSH_SOMI)S
Delay from master deasserting SPI1_SCS to slave 3-stating SPI1_SOMI P+15 P+17 P+19 ns
(1) These parameters are in addition to the general timings for SPI slave modes (Table 6-77).
(2) P = SYSCLK2 period; M = t
c(SPC)M
(SPI master bit clock period)
(3) Figure shows only Polarity = 0, Phase = 0 as an example. Table gives parameters for all four slave clocking modes.
Table 6-83. Additional
(1)
SPI1 Slave Timings, 5-Pin Option
(2)(3)
NO. PARAMETER
1.3V, 1.2V 1.1V 1.0V
UNIT
MIN MAX MIN MAX MIN MAX
25 t
d(SCSL_SPC)S
Required delay from SPI1_SCS asserted at slave to first
SPI1_CLK edge at slave.
P+1.5 P+1.5 P+1.5 ns
26 t
d(SPC_SCSH)S
Required delay from final
SPI1_CLK edge before SPI1_SCS
is deasserted.
Polarity = 0, Phase = 0,
from SPI1_CLK falling
0.5M+P+4 0.5M+P+5 0.5M+P+6
ns
Polarity = 0, Phase = 1,
from SPI1_CLK falling
P+4 P+5 P+6
Polarity = 1, Phase = 0,
from SPI1_CLK rising
0.5M+P+4 0.5M+P+5 0.5M+P+6
Polarity = 1, Phase = 1,
from SPI1_CLK rising
P+4 P+5 P+6
27 t
ena(SCSL_SOMI)S
Delay from master asserting SPI1_SCS to slave driving
SPI1_SOMI valid
P+15 P+17 P+19 ns
28 t
dis(SCSH_SOMI)S
Delay from master deasserting SPI1_SCS to slave 3-stating
SPI1_SOMI
P+15 P+17 P+19 ns
29 t
ena(SCSL_ENA)S
Delay from master deasserting SPI1_SCS to slave driving
SPI1_ENA valid
15 17 19 ns