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TMS320C6748
SPRS590G –JUNE 2009–REVISED JANUARY 2017
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Device Comparison Copyright © 2009–2017, Texas Instruments Incorporated
Table 3-10. DDR2/mDDR Terminal Functions (continued)
SIGNAL
TYPE
(1)
PULL
(2)
DESCRIPTION
NAME NO.
DDR_DQM[0] W13 O IPD
DDR2 data mask outputs
DDR_DQM[1] R10 O IPD
DDR_DQS[0] T14 I/O IPD
DDR2 data strobe inputs/outputs
DDR_DQS[1] V11 I/O IPD
DDR_BA[2] U8 O IPD
DDR2 SDRAM bank addressDDR_BA[1] T9 O IPD
DDR_BA[0] V8 O IPD
DDR_DQGATE0 R11 O IPD
DDR2 loopback signal for external DQS gating.
Route to DDR and back to DDR_DQGATE1 with
same constraints as used for DDR clock and data.
DDR_DQGATE1 R12 I IPD
DDR2 loopback signal for external DQS gating.
Route to DDR and back to DDR_DQGATE0 with
same constraints as used for DDR clock and data.
DDR_ZP U12 O —
DDR2 reference output for drive strength calibration
of N and P channel outputs. Tie to ground via 50
ohm resistor @ 5% tolerance.
DDR_VREF R6 I —
DDR voltage input for the DDR2/mDDR I/O buffers.
Note even in the case of mDDR an external resistor
divider connected to this pin is necessary.
DDR_DVDD18
N6, N9, N10,
P7, P8, P9,
P10, R7, R8,
R9
PWR — DDR PHY 1.8V power supply pins
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