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TMS320C6748
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SPRS590G –JUNE 2009–REVISED JANUARY 2017
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Peripheral Information and Electrical SpecificationsCopyright © 2009–2017, Texas Instruments Incorporated
Table 6-10. PSC1 Default Module Configuration
LPSC
Number
Module Name Power Domain Default Module State Auto Sleep/Wake Only
0 EDMA3 Channel Controller 1 AlwaysON (PD0) SwRstDisable —
1 USB0 (USB2.0) AlwaysON (PD0) SwRstDisable —
2 USB1 (USB1.1) AlwaysON (PD0) SwRstDisable —
3 GPIO AlwaysON (PD0) SwRstDisable —
4 UHPI AlwaysON (PD0) SwRstDisable —
5 EMAC AlwaysON (PD0) SwRstDisable —
6 DDR2 (and SCR_F3) AlwaysON (PD0) SwRstDisable —
7 McASP0 ( + McASP0 FIFO) AlwaysON (PD0) SwRstDisable —
8 SATA AlwaysON (PD0) SwRstDisable —
9 VPIF AlwaysON (PD0) SwRstDisable —
10 SPI 1 AlwaysON (PD0) SwRstDisable —
11 I2C 1 AlwaysON (PD0) SwRstDisable —
12 UART 1 AlwaysON (PD0) SwRstDisable —
13 UART 2 AlwaysON (PD0) SwRstDisable —
14 McBSP0 ( + McBSP0 FIFO) AlwaysON (PD0) SwRstDisable —
15 McBSP1 ( + McBSP1 FIFO) AlwaysON (PD0) SwRstDisable —
16 LCDC AlwaysON (PD0) SwRstDisable —
17 eHRPWM0/1 AlwaysON (PD0) SwRstDisable —
18 MMCSD1 AlwaysON (PD0) SwRstDisable —
19 uPP AlwaysON (PD0) SwRstDisable —
20 ECAP0/1/2 AlwaysON (PD0) SwRstDisable —
21 EDMA3 Transfer Controller 2 AlwaysON (PD0) SwRstDisable —
22 — — — —
23 — — — —
24 SCR_F0 (and bridge F0) AlwaysON (PD0) Enable Yes
25 SCR_F1 (and bridge F1) AlwaysON (PD0) Enable Yes
26 SCR_F2 (and bridge F2) AlwaysON (PD0) Enable Yes
27 SCR_F6 (and bridge F3) AlwaysON (PD0) Enable Yes
28 SCR_F7 (and bridge F4) AlwaysON (PD0) Enable Yes
29 SCR_F8 (and bridge F5) AlwaysON (PD0) Enable Yes
30 Bridge F7 (DDR Controller path) AlwaysON (PD0) Enable Yes
31 On-chip RAM (including SCR_F4
and bridge F6)
PD_SHRAM Enable —
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