Thytronic SIF5600 - Page 79

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SIF5600 - Manual - 03 - 2008
bit 0 Stack overflow
bit 1 reserved
bit 2 Eeprom overflow
bit 3 Eeprom CAL fail
bit 4 Eeprom PAR fail
bit 5 Eeprom REE fail
bit 6 reserved
bit 7 reserved
bit 8 HW fail
bit 9 Coil fail
bit 10 PW break Blin1
bit 11 reserved
bit 12 PW shorted
bit 13 CB fail
Dimension : 3 registers
Synopsis : class RREG -> ADR=3 (NUM=4), DIM=3
RREG NUM=5 Description : Clock
Framing:
INT [ 1] Year
2000,2099 step 1
INT [ 2] Month
1,12 step 1
INT [ 3] Day
1,31 step 1
INT [ 4] Hour
0,23 step 1
INT [ 5] Minute
0,59 step 1
INT [ 6] Second
0,59 step 1
INT [ 7] Millisecond
0,999 step 1
Dimension: 7 registers
Synopsis: class RREG -> ADR=4 (NUM=5), DIM=7
RREG NUM=6 Description: Event-buffer info
Framing:
INT [ 1] Events stored
0,8 step 1
INT [ 2] Last event
0,8 step 1
Dimension : 2 registers
Synopsis : class RREG -> ADR=5 (NUM=6), DIM=2
RREG NUM=7 Description : Event 1
Framing:
ENUM[ 1] E1 Reading
0 Relative
1 Direct
LONG[ 2] E1 IL1r (see IL1)
LONG[ 4] E1 IL2r (see IL2)
LONG[ 6] E1 IL3r (see IL3)
LONG[ 8] E1 IEr (see IE)
ENUM[10] E1 Cause
0 None
1 Start I>
2 Start I>>
3 Start IE>
4 Start IE>>
5 Trip I>
6 Trip I>>
7 Trip IE>
8 Trip IE>>
B16 [11] E1 Phases
bit 0 IL1
bit 1 IL2
bit 2 IL3
ENUM[12] E1 Blin1r
0 Off
1 On
ENUM[13] E1 Blout1-2r
0 Off
1 On
INT [14] E1 Year