General Procedures / Information
6-54 12/04 FaxCentre F110
GP 21 LSU
Refer to WD 4
The LSU includes the polygon motor, the laser diode, the sensor for line synchronisation and the
lens to correct the beam distortion created by the polygon motor.The motor is driven at 11295,32
rpm, and the clock frequency is 1129.532Hz.
The CLK clock is synchronised with the video clock. The frequency of the video clock is
10.22MHz.
HSYNC generation
In order to generate the horizontal synchronisation for the output pixel block, it is necessary to
switch on the LED when the beam is in the area of the optical sensor.
Figure 1
The nominal main clock is set at 92Mhz. The base clock used by the Pixel Output section is set
to Mainclock / 4 = 23MHz.
The parameter Ack_Assert in the register PO_COUNT_CONTROL is set to 1 which gives a video
clock of 11,5MHz(Base Clock / 2).
VDO1
HSYNC
PCLOCK
VDO2
1/4 rotation of the motor = 1 line = 328,95mm = 7770 dots
= 15540 base clock cycles 675.64(@23MHz)
Visible area 216 mm = 5102 dots =
40816 main clock cycle = 443.68us(@92MHz)
(283,4-216)/2=33,7mm
796dot = 77.86us(@92MHz)
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