General Procedures / Information
6-62 12/04 FaxCentre F110
EPLD
Hsync generation
This block is composed of two parts. The first one is a 14bits-shift register and the second one a
14bits decounter.
The 14bits-shift register is loaded using the signal data in (DI), clock (CLK) and chip select (CS).
The 14bits decounter is loaded with the value stored in the shift register on the falling edge of
HSYNC. On the rising edge of HSYNC, the counter starts decounting. When it reaches 0, the out-
put(VDO1) is set to 1. When decounting the output is set to 0. After reset the output is set to 1.
To enable printing, the firmware should load the shift register with the proper value and then set
LDEN. The laser will then be switched on permanently until the decounter gets the first falling edge
on HSYNC. After the first line, the counter is automatically reloaded and restarted at each end of
line.
Smartcard and ADC mutiplexing
The EPLD filters all signals coming from the Digicolor during ADC operations and disable the ADC
during smartcard operations.
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