Xilinx KC705

KC705 Evaluation Board 8
UG810 (v1.8) March 20, 2018 www.xilinx.com
Chapter 1: KC705 Evaluation Board Features
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User pushbuttons (five directional)
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CPU reset pushbutton
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User DIP switch (4-pole GPIO)
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User edge drive rotary encoder switch
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User SMA GPIO connectors (one pair)
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LCD character display (16 characters x 2 lines)
•Switches
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Power on/off slide switch
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FPGA_PROG_B pushbutton switch
• VITA 57.1 FMC HPC Connector
• VITA 57.1 FMC LPC Connector
• Power management
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PMBus voltage and current monitoring via TI power controller
• XADC header
• Configuration options
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Linear BPI flash memory
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Quad SPI flash memory
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USB JTAG configuration port
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Platform cable header JTAG configuration port
The KC705 board block diagram is shown in Figure 1-1. The KC705 board schematics are
available for download from the Kintex-7 FPGA KC705 Evaluation Kit website.
CAUTION! The KC705 board can be damaged by electrostatic discharge (ESD). Follow standard ESD
prevention measures when handling the board.
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