RocketIO™ Transceiver User Guide www.xilinx.com UG024 (v3.0) February 22, 2007
02/22/07 3.0 • “Example 1a: Two-Byte Clock with DCM,” page 43: Corrected code in
TWO_BYTE_CLK definition (VHDL).
• “Example 2: Four-Byte Clock,” page 46: Corrected code in DCM instantiation
(VHDL).
• “RX_LOSS_OF_SYNC_FSM,” page 77: Added note that PLL must be locked for
attribute values to be valid.
• “CRC Operation,” page 84: Added CRC logic start state on reset.
• “Power Conditioning,” page 109: Fixed broken link to Data Sheet DS083.
• “Passive Filtering,” page 111: Corrected part number of Murata ferrite bead.
• “Pletronics LV1145B (LVDS Outputs),” page 119: Corrected I/O standard name to
LVDS_25_DT.
• “Powering the RocketIO Transceivers,” page 120: Added section “Pin Connections on
the Unused RocketIO Transceivers.”
• “The POWERDOWN Port,” page 120: Added that toggling POWERDOWN properly
initializes the PMA.
• “HSPICE,” page 121 and “Characterization Reports,” page 149: Fixed obsolete links
to SPICE Model and Characterization Report web pages.
• Figure 2-12: In 8B/10B Data Flow block diagram, moved Comma Detect function
from PMA to PCS.
• Table 3-4:
♦ Corrected REFCLK/BREFCLK typical rise/fall time from 400 ps to 600 ps.
♦ Corrected TLOCK acquisition time from Typ to Max.
• Table 3-5: Corrected voltage range in heading to 1.6V–1.8V.
• Table B-1: Corrected data characters D18.2, D09.3, D10.3, D18.5, and D18.6.
Date Version Revision
Product Not Recommended for New Designs
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