Xilinx RocketIO User Manual

UG024 (v3.0) February 22, 2007 www.xilinx.com RocketIO™ Transceiver User Guide
02/24/04 2.3 • Table 2-3, page 41: Added FG676 row to BREFCLK Pin Numbers.
• Figure 2-4, page 47: Added note above Figure 2-4 stating, “These local MGT clock
input inverters, shown and noted in Figure 2-4, are not included in the
FOUR_BYTE_CLK templates.
• Section“RXRECCLK” in Chapter 2: Added paragraph to section explaining how
RXRECCLK changes monotonically and how the recovered bit clock is derived.
• Section “Data Path Latency” in Chapter 2: Revised first sentence to read: “With the
many configurations of the MGT, both the transmit and receive data path latencies
vary.”
• Section “RXBUFSTATUS” in Chapter 2: Revised the description of RXBUFSTATUS.
• Figure 3-1, page 103: Replaced old Figure 3-1, page 101, with new Figure 3-1 showing
“Differential Amplifier.”
• Figure 3-6, page 107: Added new Figure 3-6, page 105, showing “MGT Receiver.”
• Table 3-4, page 108: Added text to CDR Parameters (TLOCK parameter in Conditions
column) and edited Note 3.
• Section “Voltage Regulation” in Chapter 3: Added Linear Technology part numbers
(LT1963A, LT1964).
• Section “Passive Filtering” in Chapter 3: Added new cap rules for RocketIO
transceiver.
• Figure 3-8, page 111: Replaced old Figure 3-8 with new figure showing “Power
Filtering Network on Devices with Internal and External Capacitors.”
• Table 3-7, page 112: Added Device and Package combinations table.
• Figure 3-9, page 113: Added new Figure 3-10, page 110, showing “Example Power
Filtering PCB Layout for Four MGTs, in Device with Internal Capacitors, Bottom
Layer.” Modified the text describing Figure 3-9, page 113.
• Figure 3-10, page 114: Replaced old Figure 3-10 with new figure showing “Example
Power Filtering PCB Layout for Four MGTs, in Device with External Capacitors, Top
Layer.” Removed the text describing old Figure 3-10.
• Figure 3-11, page 115: Replaced old Figure 3-11 with new figure showing “Example
Power Filtering PCB Layout for Four MGTs, in Device with External Capacitors,
Bottom Layer.” Removed the text describing old Figure 3-11.
• Table 3-8, page 118: Added V
TRX
and V
TTX
voltages for different coupling
environments.
05/20/04 2.3.1 • Changed the value of TRCLK/RFCLK in Table 3-4.
06/24/04 2.3.2 • Modified Figure 2-3.
08/25/04 2.4 • Fixed error in Hex value in Table 2-15, page 74.
• Add application notes to Appendix C, “Related Online Documents.”
• Replaced “Voltage Regulation” section with
“Voltage Regulator Selection and Use” in Chapter 3.
• Removed all references to the XCVP125 device.
• Modified Note 4 in Table 3-5.
12/09/04 2.5 • Added PCI Express and new note to Table 1-2. Added sentence to REFCLK definition
in Table 1-5. Updated Table 3-5.
• Fixed typo in “Epson EG-2121CA 2.5V (LVPECL Outputs),” page 119.
• Added XAPP572 to Appendix C, “Related Online Documents” and added references
to XAPP572 inTable 1-6 (under SERDES_10B description) and “Half-Rate Clocking
Scheme,” page 54.
Date Version Revision
Product Not Recommended for New Designs

Xilinx RocketIO Specifications

General

Brand	Xilinx
Model	RocketIO
Category	Transceiver
Language	English