Xilinx RocketIO User Manual

RocketIO™ Transceiver User Guide www.xilinx.com UG024 (v3.0) February 22, 2007
06/12/03 2.1 • Table 1-2: Added qualifying footnote to XAUI 10GFC.
• Table 1-5: Corrected definition of RXRECCLK.
• Section “RocketIO Transceiver Instantiations” in Chapter 1: added text briefly
explaining what the Instantiation Wizard does.
• Table 2-14: Changed numerics from exact values to rounded-off approximations
(nearest 5,000), and added footnote calling attention to this.
• Section “Clocking” in Chapter 2: added text recommending use of an IBUFGDS for
reference clock input to FPGA fabric.
• Section “RXRECCLK” in Chapter 2: Deleted references to SERDES_10B attribute and
to divide-by-10. (RXRECCLK is always 1/20th the data rate.).
• Section “CRC_FORMAT” in Chapter 2: Corrected minimum data length for
USER_MODE to “greater than 20”.
• Table 3-5: Clarified the significance of the V
TTX
/V
TRX
voltages shown in this table.
• Section “AC and DC Coupling” in Chapter 3: Explanatory material added regarding
V
TRX
/V
TTX
settings when AC or DC coupling is used.
• Table 4-1: Corrected pinouts for FG256 and FG456.
• Table 4-3: Corrected pinouts for FF1517 (XC2VP70).
11/07/03 2.2 • Section “Clock Signals” in Chapter 2: Added material that states:
♦ the reference clock must be provided at all times.
♦ any added jitter on the reference clock will be reflected on the RX/TX I/O.
• Figure 2-3: Added a BUFG after the IBUFGDS reference clock buffer.
• Section “RX_BUFFER_USE” in Chapter 2: Corrected erroneous “USRCLK2” to
“RXUSRCLK/RXUSRCLK2”.
• Table 2-20: Added footnotes qualifying the maximum receive-side latency parameters
given in the table.
• Section “FIBRE_CHAN” in Chapter 2: Added specification for minimum data length
(24 bytes not including CRC placeholder).
• Section “ETHERNET” in Chapter 2: Added note indicating that Gigabit Ethernet 802.3
frame specifications must be adhered to.
• Table 2-23: Corrected “External” to “Internal” loopback. Improved explanation of
Parallel Mode loopback.
• Added Figure 2-28, “Serial and Parallel Loopback Logic.”
• Section “Clock and Data Recovery” in Chapter 3: Corrected text to make clear that
RXRECCLK is always 1/20th the incoming data rate, and that CDR requires a
minimum number of transitions to achieve and maintain a lock on the received data.
• Section “Voltage Regulation” in Chapter 3: Added material defining voltage regulator
requirements when a device other than the LT1963 is used.
• Section “AC and DC Coupling” in Chapter 3: Added footnote to Table 3-8 clarifying
V
TRX
/V
TTX
voltage compliance.
• Figure 3-17 and section “Epson EG-2121CA 2.5V (LVPECL Outputs)” in Chapter 3:
Added material specifying the optional use of an LVPECL buffer as an alternative to
the LVDS buffer previously specified.
• Table 4-2: Added pinouts for FG676 package, XC2VP20 and XC2VP30.
• Table A-5: Added BREFCLK parameters T
BREFPWH
and T
BREFPWL
.
• Section “Application Notes” in Appendix C: Included new Xilinx Application Notes
XAPP648, XAPP669, and XAPP670.
• Various non-technical edits and corrections.
Date Version Revision
Product Not Recommended for New Designs

Xilinx RocketIO Specifications

General

Brand	Xilinx
Model	RocketIO
Category	Transceiver
Language	English