Xilinx VCU118

VCU118 Board User Guide 157
UG1224 (v1.0) December 15, 2016
www.xilinx.com
Appendix B: Master Constraints File Listing
set_property IOSTANDARD LVCMOS12 [get_ports "GPIO_LED5"];
set_property PACKAGE_PIN AV36 [get_ports "GPIO_LED6"];
set_property IOSTANDARD LVCMOS12 [get_ports "GPIO_LED6"];
set_property PACKAGE_PIN BA37 [get_ports "GPIO_LED7"];
set_property IOSTANDARD LVCMOS12 [get_ports "GPIO_LED7"];
# GPIO PB SWITCHES
set_property PACKAGE_PIN BD23 [get_ports "GPIO_SW_C"];
set_property IOSTANDARD LVCMOS18 [get_ports "GPIO_SW_C"];
set_property PACKAGE_PIN BE23 [get_ports "GPIO_SW_E"];
set_property IOSTANDARD LVCMOS18 [get_ports "GPIO_SW_E"];
set_property PACKAGE_PIN BB24 [get_ports "GPIO_SW_N"];
set_property IOSTANDARD LVCMOS18 [get_ports "GPIO_SW_N"];
set_property PACKAGE_PIN BE22 [get_ports "GPIO_SW_S"];
set_property IOSTANDARD LVCMOS18 [get_ports "GPIO_SW_S"];
set_property PACKAGE_PIN BF22 [get_ports "GPIO_SW_W"];
set_property IOSTANDARD LVCMOS18 [get_ports "GPIO_SW_W"];
# CPU RESET GPIO PB SWITCH
set_property PACKAGE_PIN L19 [get_ports "CPU_RESET"];
set_property IOSTANDARD LVCMOS12 [get_ports "CPU_RESET"];
# PMOD0
set_property PACKAGE_PIN AY14 [get_ports "PMOD0_0_LS "];
set_property IOSTANDARD LVCMOS12 [get_ports "PMOD0_0_LS "];
set_property PACKAGE_PIN AY15 [get_ports "PMOD0_1_LS "];
set_property IOSTANDARD LVCMOS12 [get_ports "PMOD0_1_LS "];
set_property PACKAGE_PIN AW15 [get_ports "PMOD0_2_LS "];
set_property IOSTANDARD LVCMOS12 [get_ports "PMOD0_2_LS "];
set_property PACKAGE_PIN AV15 [get_ports "PMOD0_3_LS "];
set_property IOSTANDARD LVCMOS12 [get_ports "PMOD0_3_LS "];
set_property PACKAGE_PIN AV16 [get_ports "PMOD0_4_LS "];
set_property IOSTANDARD LVCMOS12 [get_ports "PMOD0_4_LS "];
set_property PACKAGE_PIN AU16 [get_ports "PMOD0_5_LS "];
set_property IOSTANDARD LVCMOS12 [get_ports "PMOD0_5_LS "];
set_property PACKAGE_PIN AT15 [get_ports "PMOD0_6_LS "];
set_property IOSTANDARD LVCMOS12 [get_ports "PMOD0_6_LS "];
set_property PACKAGE_PIN AT16 [get_ports "PMOD0_7_LS "];
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