Name: Xilinx VCU118
Brand: Xilinx
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VCU118 Board User Guide 158

UG1224 (v1.0) December 15, 2016

www.xilinx.com

Appendix B: Master Constraints File Listing

set_property IOSTANDARD LVCMOS12 [get_ports "PMOD0_7_LS "];

# PMOD1

set_property PACKAGE_PIN N28 [get_ports "PMOD1_0_LS "];

set_property IOSTANDARD LVCMOS12 [get_ports "PMOD1_0_LS "];

set_property PACKAGE_PIN M30 [get_ports "PMOD1_1_LS "];

set_property IOSTANDARD LVCMOS12 [get_ports "PMOD1_1_LS "];

set_property PACKAGE_PIN N30 [get_ports "PMOD1_2_LS "];

set_property IOSTANDARD LVCMOS12 [get_ports "PMOD1_2_LS "];

set_property PACKAGE_PIN P30 [get_ports "PMOD1_3_LS "];

set_property IOSTANDARD LVCMOS12 [get_ports "PMOD1_3_LS "];

set_property PACKAGE_PIN P29 [get_ports "PMOD1_4_LS "];

set_property IOSTANDARD LVCMOS12 [get_ports "PMOD1_4_LS "];

set_property PACKAGE_PIN L31 [get_ports "PMOD1_5_LS "];

set_property IOSTANDARD LVCMOS12 [get_ports "PMOD1_5_LS "];

set_property PACKAGE_PIN M31 [get_ports "PMOD1_6_LS "];

set_property IOSTANDARD LVCMOS12 [get_ports "PMOD1_6_LS "];

set_property PACKAGE_PIN R29 [get_ports "PMOD1_7_LS "];

set_property IOSTANDARD LVCMOS12 [get_ports "PMOD1_7_LS "];

# PCIE

set_property PACKAGE_PIN AM17 [get_ports "PCIE_PERST_LS"];

set_property IOSTANDARD LVCMOS18 [get_ports "PCIE_PERST_LS"];

set_property PACKAGE_PIN BC24 [get_ports "PCIE_WAKE_B_LS"];

set_property IOSTANDARD LVCMOS18 [get_ports "PCIE_WAKE_B_LS"];

# FAN

set_property PACKAGE_PIN BA10 [get_ports "SM_FAN_PWM "];

set_property IOSTANDARD LVCMOS18 [get_ports "SM_FAN_PWM "];

set_property PACKAGE_PIN BF7 [get_ports "SM_FAN_TACH"];

set_property IOSTANDARD LVCMOS18 [get_ports "SM_FAN_TACH"];

# MAXIM CABLE

set_property PACKAGE_PIN BF40 [get_ports "MAXIM_CABLE_LS_B"];

set_property IOSTANDARD LVCMOS12 [get_ports "MAXIM_CABLE_LS_B"];

# PMBUS

set_property PACKAGE_PIN BB23 [get_ports "PMBUS_ALERT_FPGA"];

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