Abov MC96F6432Q User Manual

MC96F6432
180 June 22, 2018 Ver. 2.9
T4ISR (Timer 4 Interrupt Status Register) : 1006H (ESFR)
7
6
5
4
3
2
1
0
IOVR
IBTM
ICMA
ICMB
ICMC
–
–
–
R/W
R/W
R/W
R/W
R/W
–
–
–
Initial value : 00H
IOVR
Timer 4 Overflow Interrupt Status, Write ‘0’ to this bit for clear
0
Overflow no occurrence
1
Overflow occurrence
IBTM
Timer 4 Bottom Interrupt Status, Write ‘0’ to this bit for clear
(In the Back-to-Back mode)
0
Bottom no occurrence
1
Bottom occurrence
ICMA
Timer 4 Compare Match or PWM A-ch Match Interrupt Status, Write ‘0’
to this bit for clear
0
Compare match or PWM A-ch match no occurrence
1
Compare match or PWM A-ch match occurrence
ICMB
Timer 4 PWM B-ch Match Interrupt Status, Write ‘0’ to this bit for clear
0
PWM B-ch match no occurrence
1
PWM B-ch match occurrence
ICMC
Timer 4 PWM C-ch Match Interrupt Status, Write ‘0’ to this bit for clear
0
PWM C-ch match no occurrence
1
PWM C-ch match occurrence
T4MSK (Timer 4 Interrupt Mask Register) : 1007H (ESFR)
7
6
5
4
3
2
1
0
OVRMSK
BTMMSK
CMAMSK
CMBMSK
CMCMSK
–
–
–
R/W
R/W
R/W
R/W
R/W
–
–
–
Initial value : 00H
OVRMSK
Control Timer 4 Overflow Interrupt
0
Disable overflow interrupt
1
Enable overflow interrupt
BTMMSK
Control Timer 4 Bottom Interrupt
0
Disable bottom interrupt
1
Enable bottom interrupt
CMAMSK
Control Timer 4 Compare Match or PWM A-ch Match Interrupt
0
Disable compare match or PWM A-ch match interrupt
1
Enable compare match or PWM A-ch match interrupt
CMBMSK
Control Timer 4 PWM B-ch Match Interrupt
0
Disable PWM B-ch match interrupt
1
Enable PWM B-ch match interrupt
CMCMSK
Control Timer 4 PWM C-ch Match Interrupt
0
Disable PWM C-ch match interrupt
1
Enable PWM C-ch match interrupt

Abov MC96F6432Q Specifications

General

Brand	Abov
Model	MC96F6432Q
Category	Microcontrollers
Language	English