Abov MC96F6432Q User Manual

MC96F6432
June 22, 2018 Ver. 2.9 227
USI0CR2 (USI0 Control Register 2: For UART, SPI, and I2C mode) : DAH
7
6
5
4
3
2
1
0
DRIE0
TXCIE0
RXCIE0
WAKEIE0
TXE0
RXE0
USI0EN
DBLS0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Initial value : 00H
DRIE0
Interrupt enable bit for data register empty (only UART and SPI mode).
0
Interrupt from DRE0 is inhibited (use polling)
1
When DRE0 is set, request an interrupt
TXCIE0
Interrupt enable bit for transmit complete (only UART and SPI mode).
0
Interrupt from TXC0 is inhibited (use polling)
1
When TXC0 is set, request an interrupt
RXCIE0
Interrupt enable bit for receive complete (only UART and SPI mode).
0
Interrupt from RXC0 is inhibited (use polling)
1
When RXC0 is set, request an interrupt
WAKEIE0
Interrupt enable bit for asynchronous wake in STOP mode. When device
is in stop mode, if RXD0 goes to low level an interrupt can be requested
to wake-up system. (only UART mode). At that time the DRIE0 bit and
USI0ST1 register value should be set to ‘0b’ and “00H”, respectively.
0
Interrupt from Wake is inhibited
1
When WAKE0 is set, request an interrupt
TXE0
Enables the transmitter unit (only UART and SPI mode).
0
Transmitter is disabled
1
Transmitter is enabled
RXE0
Enables the receiver unit (only UART and SPI mode).
0
Receiver is disabled
1
Receiver is enabled
USI0EN
Activate USI0 function block by supplying.
0
USI0 is disabled
1
USI0 is enabled
DBLS0
This bit selects receiver sampling rate (only UART).
0
Normal asynchronous operation
1
Double Speed asynchronous operation

Abov MC96F6432Q Specifications

General

Brand	Abov
Model	MC96F6432Q
Category	Microcontrollers
Language	English