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Chapter 3: Testing Logic Analyzer Performance
To ensure the 16753/54/55/56A or 16950A logic analyzer (also referred to as the
module or the card) is operating as specified, software tests (self-tests) and a
manual performance test are done. The logic analyzer is considered performance-
verified if all of the software tests and the manual performance test have passed.
The specifications for the 16753/54/55/56A and 16950A logic analyzer define a
minimum master to master clock time and a minimum data eye width at which
data can be acquired. The manual performance test (minimum master-to-master
clock time and minimum eye width test) verifies that the logic analyzer meets
these specifications.
Mainframes
The 16753/54/55/56A logic analyzer modules can be tested in either a 16900-
series mainframe or a 16700-series mainframe.
The 16950A logic analyzer module must be tested in a 16900-series mainframe.
In either case, the SMA/Flying Lead Test Connectors, the equipment required,
and setup of the test equipment will be the same, except that the logic analyzer
setup will differ.
The general instructions for performance test begin on page 23 with instructions
for assembling the test connectors. Instructions specific to testing the module in
a 16900-series mainframe begin on
page 37. Instruction specific to testing the
module in a 16700-series mainframe begin on page 61.
Test Strategy
Only specified parameters are tested. Specifications are listed on page 11. The
test conditions defined in this procedure ensure that the specified parameter is
as good as or better than specifications. No attempt is made to determine
performance which is better than specifications. Not all channels of the logic
analyzer will be tested; a sample of channels is tested. The calibration laboratory
may choose to elaborate on these tests and test all channels at their discretion.
Eye Finder is used to adjust the sampling position on every channel. Eye Finder
must be used to achieve minimum data eye width performance.
First, the logic analyzer will be tested in the 300 Mb/s state mode. Then it will be
tested in the 600 Mb/s state mode.
In the 300 Mb/s state mode all four clocks (Clk1, Clk2, Clk3 and Clk4) will be
tested with their respective pods.
The 600 Mb/s mode has only one clock (Clk1). All tests in the 600 Mb/s mode will
use clock Clk1.
All four pods will be tested, one pod at a time, in both 300 Mb/s state mode and
600 Mb/s state mode.
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