276 34980A User’s Guide
10 64-Bit Digital I/O Module with Memory and Counter
Optionally, you can provide an external strobe input on the H2 line to
control the memory transfers. If you pace the memory inputs from an
external clock, the 34950A will sense the leading edge of the strobe and
set the data. The data will be valid after T
PD
and the receiving device may
latch the data. T
PD
ranges from 140 ns to 60 ns. The maximum T
PD
of
140 ns limits operation in this mode to 7 MHz.
A synchronous buffered output using an external clock is shown in the
diagram below (default handshake line polarity).
For example, using the internal strobe, the following SCPI commands set
a 34950A in slot 5 to have a 32- bit output using synchronous handshake.
The number of times to output the traces is set to 4. A trace is then
loaded into memory and assigned to the channel. The memory is enabled
and then triggered. The start/stop line is set high following the first byte
handshake and remains high until the last byte is output.
CONF:DIG:WIDT LWOR, (@5101)
CONF:DIG:DIR OUTP, (@5101)
CONF:DIG:HAND SYNC, (@5101)
SOUR:DIG:MEM:NCYC 4, (@5101)
TRAC:DATA:DIG:LWOR (@5101), mytrace, #hFFEEFFEE, #hBCBC9999
SOUR:DIG:MEM:TRAC mytrace,(@5101)
SOUR:DIG:MEM:ENAB ON, (@5101)
SOUR:DIG:MEM:STAR (@5101)
Using an external strobe, the following SCPI commands set a 34950A in
slot 5 to have an 8- bit output using synchronous handshake with an
external strobe input. The number of times to output the traces is set to
infinite (continuous output until the memory is stopped). The memory is
enabled and then triggered. The start/stop line is set high following the
first byte handshake and remains high until the last byte is output.
CONF:DIG:WIDT BYTE, (@5101)
CONF:DIG:DIR OUTP, (@5101)
CONF:DIG:HAND SYNC, (@5101)
CONF:DIG:HAND:SYNC:STR:SOUR EXT, (@5101)
SOUR:DIG:MEM:NCYC 0, (@5101)
TRAC:DATA:DIG:BYTE (@5101), mytrace, 260, 139
SOUR:DIG:MEM:TRAC mytrace,(@5101)
SOUR:DIG:MEM:ENAB ON, (@5101)
SOUR:DIG:MEM:STAR (@5101)
H0 (Start/Stop)
H2 (Clock In)
Data Ou t
Valid
T
CYCLE
(Last Cycle)
Invalid
T
PD
T
PD
T
PD