Agilent Technologies ESG-D Series User Manual

A14 CPU/MOTHERBOARD BLOCK DIAGRAM (1 OF 2)
A14 CPU/MOTHERBOARD BLOCK DIAGRAM (1 0F 2)
sk7113a
CPU CLOCK
CPU INTERFACE
MEMORY
CPU
SERIAL INTERFACE
(EXTERNAL)
SERIAL INTERFACE
(INTERNAL)
ATTENUATOR
& RPP INTERFACE
DIGITAL SIGNAL
PROCESSOR (DSP)
32.77 kHz
CLOCK
RS-232
SERIAL
INTERFACE
+5V
J8-2
J8-8
J8-3
J8-7
J8-4
J8-5
RECV
CTS
XMIT
RTS
+5V
IRQ 1
IRQ2
IRQ3
IRQ4
IRQ5
IRQ6
IRQ7
TP CLK
TPU 0
TPU1
TPU2
TPU3
TPU4
TPU5
TPU6
TPU7
TPU8
TPU10
L SERIAL I/O INT
NOT USED
L HP-IB INT
L RPG INT
NOT USED
L KEY INT
NOT USED
10 MHz DIG
COUNTER
CPU TRIG INT
L DSP INT
DIG BUS INT 1
DIG BUS INT 2
DIG BUS INT 3
DIG BUS INT 4
PULSE INT
L RPP INT
CTS
RXD
TXD
L PRESET
L HALT
INTERNAL
DATA BUS
FLASH PROGRAM
VOLTAGE
SWITCH &
LEDS
INTERNAL
DATA BUS
INTERNAL
DATA BUS
ENABLE
FLASH
PROGRAM
VOLTAGE
REG
+15V
FLASH
VPP
TP303
PROGRAM = +12V
SELF TEST
LEDS
CONFIG
SWITCH
INT ADDR
BUS
SERIAL I/O
BUS
SERIAL I/O
INTERFACE
FROM: AUXILIARY
INTERFACE
TO: DAUGHTER
BOARD
J5-24
J5-21
J5-18
J5-26
J5-23
J5-20
J5-76
J5-73
J5-70
J14-17
J14-11
J14-10
J14-9
J14-7
J14-6
J14-5
J14-4
J14-3
J14-2
J14-20
J14-19
J14-18
J14-12
J14-16
J14-1
J14-14
J14-15
J14-13
J14-8
HP-IB
INTERFACE
INTERNAL
DATA BUS
INT ADDR
BUS
HP-IB
INTERFACE
LATN
L EOI
L SRQ
L REN
L IFC
L DAV
NDAC
NRFD
DIO1
DIO2
DIO3
DIO4
DIO5
DIO6
DIO7
DIO8
TO:
HP-IB
J7-11
J7-5
J7-10
J7-17
J7-9
J7-6
J7-8
J7-7
J7-1
J7-2
J7-3
J7-4
J7-13
J7-14
J7-15
J7-16
L HP-IB INT
L SERIAL
I/O INT
DACDAC
DACDAC
ABUS
INT MOD
ADDRESS
BUFFERS
DATA
BUFFERS
BUS
CONTROL
BOOT
ROM
ADDRESS BUS
CPU DATA BUS
SERIAL I/O BUS
CPU DATA BUS
INT CONT
BUS
MEM ADDR
BUS
MEM DATA
BUS
INT ADDR
BUS
INTERNAL DATA
BUS
FLASH
MEMORY
1M X 16
EEROM
64K X 8
NONVOLATILE
RAM
128K X 16
RAM
128K X 16
MEM ADDR
BUS
MEM ADDR
BUS
MEM ADDR
BUS
MEM ADDR
BUS
MEM DATA
BUS
MEM DATA
BUS
MEM DATA
BUS
MEM DATA
BUS
REF ENABLE
REF CLK
REF DATA
SYNTH ENABLE
SYNTH CLK
SYNTH DATA
OUTPUT ENABLE
OUTPUT CLK
OUTPUT DATA
L = LF ATTEN
L = HF ATTEN
ATTEN 40B
ATTEN 5A
ATTEN 10A
ATTEN 10B
ATTEN 40A
ATTEN 5B
ATTEN 20
ATTEN XX
ATTEN ENABLE
ATTEN CLK
ATTEN DATA
L RPP INT
L RPP RESET
ATTEN ENABLE
ATTEN CLK
ATTEN DATA
L DCC ALT
PWR SEL
TRIG INT
INTERNAL DATA BUS
HF
ATTEN
CONTROL
ATTEN
SENSE
+15V
+12.5V
+5.2V
-12.5V
ACOM
L RPP INT
L RPP RESET
INTERNAL MODULATION
DAC
TRIGGER I/O
10 MHz IN/OUT
CPU TRIG OUT
DCC TRIG OUT
DSP TRIG OUT
CPU TRIG INT
DCC TRIG INT
TRIG INT
TRIG
ENABLE
TRIG
ENABLE
TRIGGER
IN
TRIGGER
IN
10 MHz
OUT
10 MHz
IN
J11
TRIGGER
OUT
J10
J12
J13
FROM:
DAUGHTER
BOARD
TO:
DAUGHTER
BOARD
DSP TRIG
OUT
L DSP INT
CLK OUT
TP701
RESET
ANALOG TO DIGITAL
CONVERTER (ADC)
TRIG INT
SWEEP RAMP
INT ADDR BUS
DSP ADDR BUS
DSP DATA BUS
INTERNAL DATA BUS
16 MHz
CLOCK
DSP/CPU
INTERFACE
DIGITAL
SIGNAL
PROCESSOR
SERIAL INTERFACE
SERIAL INTERFACE
DSP ADDR BUS
DSP RAM
DSP DATA BUS
DSP
RAM
32K X 8
+
+
SWEEP
OUT
J9
TP705
TP706
TO: DAUGHTER
BOARD
+10V REF
SWEEP RAMP
A BUS
BUF ABUS
BUF ABUS
ABUS
ABUS RTN
TP703
TP702
ADC IN
TP704
+5V
ADC

Agilent Technologies ESG-D Series Specifications

General

Brand	Agilent Technologies
Model	ESG-D Series
Category	Portable Generator
Language	English