Agilent Technologies ESG-D Series User Manual

A7 BASEBAND GENERATOR BLOCK DIAGRAM (OPTION IEH)
A7 BASEBAND GENERATOR BLOCK DIAGRAM (OPTION IEH)
sk784a
DAC
I DATA GENERATION
ANALOG FILTERS
(NADC/PDC
PHS GSM)
π
WRITE DATA
LATCH I CAL
12
12
FORMAT SELECT
CONTROL LOGIC
/4 CLK
FORMAT SELECT
CA ADDRESS & CONTROL
I
CAL LATCHES
I
/4 DQPS
(NADC, PHS,
PDC)
π
I
CONSTANT AMPL
(GMSK, GFSK)
ABUS
I OUT
P405
I OUT
PATH CONTROL
LOGIC
I DAC
DATA
MODULATION
ENABLE/SELECT
TO I-OUT
INT I MOD OUT
P301-2
Q DATA GENERATION
WRITE DATA
LATCH Q CAL
12
Q
CAL LATCHES
Q OUT
π
π
12
FORMAT SELECT
/4 CONTROL LOGIC
/4 CLK
FORMAT SELECT
CA ADDRESS & CONTROL
Q
/4 DQPSK
π
Q
CONSTANT AMPL
(GMSK, GFSK)
Q DAC
DATA
MODULATION
ENABLE/SELECT
MOD
INVERT
DAC
ANALOG FILTERS
(NADC/PDC
PHS GSM)
ABUS
PATH CONTROL
LOGIC
MOD INVERT
P404
Q OUT
TO I-OUT
INT Q MOD OUT
P301-53
INTERNAL DATA GENERATOR
INTERNAL DATA
GENERATOR
(PATTERN RAM=1M
INTERNAL SYNC
INTERNAL DATA
PATTERN TRIG
FROM PATTERN TRIG IN
P300-4
PLL BUF BIT CLK
EVENT SELECT
INTERNAL BURST
INTERNAL ALT POWER
P300-10
EVENT 2
TO EVENT 2
EVENT 1
TO EVENT 1
P300-8
ABUS
BURST
BURST MOD
BURST MOD
SWITCH
AND
FILTERS
BURSTPLS
BURST
CONTROL LOGIC
P301-59
P301-80
L DCC ALT PWR SEL
INTL ALC HOLD
BURST PULSE
BURST ENVELOPE
P301-31
P301-30
P301-57
+PTAT
EEPROM
DATA
LATCHED
ADDRESS
LATCHED
DATA
CONTROL
LOGIC
DIGITAL INTERFACE
P301-33
EXT SELECT
L EXT STROBE
P301-82
P301-83
EXT RD L WR
EXT RESET
P301-32
P301-24
IAB0
IAB1
P301-74
P301-25
IAB2
IAB3
P301-26
P301-76
IAB4
IAB5
P301-27
P301-77
IAB6
IAB7
P301-78
P301-29
IAB8
IAB9
P301-79
P301-36
IAB10
READ/LWRITE
STROBE
SELECT
RESET
A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10
P301-19
EXT_DO
EXT_D1
P301-20
P301-70
EXT_D2
EXT_D3
P301-21
P301-71
EXT_D4
EXT_D5
P301-72
P301-23
EXT_D6
P301-73
EXT_D7
D0
DIG BUS INT
(PLL UNLOCKED)
D1
D2
D3
D4
D5
D6
D7
SELECT
CLK
PLL BUF BIT CLK
PLL LOCK SIG
PLL REF
DATA SWITCH
π
DATA GENERATION CONTROL
LOOP
COUNT
&
DIFF
ENCODE
INTERNAL
CLK
MASTER CLOCK
BIT CLOCK INV
BUFFERED DATA
SYMBOL SYNC INV
PMF CONTROL
CONTROL
LOGIC
BURST
CONTROL LOGIC
BURST PLS
MOD INVERT
CAL ENABLE
LATCH I CAL
LATCH Q CAL
PLL GAIN
EXT REF ENABLE
/4 PMF ENABLE
CA PMF ENABLE
VCO ENABLE
EVENT SELECT
PATH
CONTROL LOGIC
PMF CONTROL
FORMAT SELECT
SUB I CLK
BIT CLK INV
LATCH ADDRESS
L BURST
LATCH DATA
π
/4 CLK
INT CLOCK
SUB I CLKS
PLL LOCK SIG
PATH
CONTROL
LOGIC
π
CA ADDRESS & CONTROL
/4 CONTROL LOGIC
REF
MASTER CLOCK PLL
ABUS
PLL TUNE
PLL_ TUNE
160 TO 320 MHz
MASTER CLOCK
20 TO
40 MHz
VCO
ENABLE
DIG BUS INT
(PLL UNLOCKED)
REFERENCE
REF SELECT
&
DIVIDE
10 MHz DIG
P301-84
FROM MOTHERBOARD
/CPU
13 MHz
FROM 13 MHz IN
P403
LOOP FILTER
&
LEAD/LAG
DATA CLOCK
FROM
DATA CLOCK
CLOCK
SELECT
INT CLOCK
P103
PLL BUF BIT CLOCK
BIT CLOCK INV
CLK OUT
FROM
SYMBOL SYNC
P300-14
TO DATA
CLK OUT
FROM
BURST GATE IN
DATA
SELECT
P100
DATA OUT
P300-12
TO DATA OUT
BUFFERED DATA
RC TIME
CONSTANT
ABUS
DATA
DATA
FROM DATA
INT DATA
SYMBOL SYNC INV
SYMBOL SYNC
SYNC
SELECT
INT SYNC
P101
P300-2
SYNC OUT
P300-12
TO SYMBOL
SYNC OUT
BURST
SELECT
BURST GATE
INT BURST
L BURST
Φ
PLL
DIVIDERS
VCO
POWER SUPPLY INPUTS
+15V
+10 VREF
ABUS
-1 VREF
-1 VREF
+32V
P301-9
P301-14,64
P301-16,66
P301-17,67
P301-12
P301-62
P301-13,63
P301-1,7,54,56
P301-22,28,34,
40,46,69,75,81,
87,93 ,99
+5VA
+5.2V
-5.2V
-5V
-15V
ANALOG
COMMON
DIGITAL
COMMON
+10V
REF

Agilent Technologies ESG-D Series Specifications

General

Brand	Agilent Technologies
Model	ESG-D Series
Category	Portable Generator
Language	English