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Alinx AX7035 - Part 7: QSPI Flash

Alinx AX7035
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ARTIX-7 FPGA Development Board AX7035 User Manual
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DDR3_A[12]
IO_L18P_T2_34
Y6
DDR3_A[13]
IO_L17P_T2_34
R6
DDR3_BA[0]
IO_L22N_T3_34
AB8
DDR3_BA[1]
IO_L15N_T2_DQS_34
W5
DDR3_BA[2]
IO_L23N_T3_34
Y7
DDR3_S0
IO_25_34
U7
DDR3_RAS
IO_L20P_T3_34
AB7
DDR3_CAS
IO_L13N_T2_MRCC_34
T4
DDR3_WE
IO_L15P_T2_DQS_34
W6
DDR3_ODT
IO_L20N_T3_34
AB6
DDR3_RESET
IO_0_34
T3
DDR3_CLK_P
IO_L21P_T3_DQS_34
V9
DDR3_CLK_N
IO_L21N_T3_DQS_34
V8
DDR3_CKE
IO_L13P_T2_MRCC_34
R4
Part 7: QSPI Flash
The AX7035 FPGA development board is equipped with one128MBit
QSPI FLASH, and the model is N25Q128, which uses the 3.3V CMOS voltage
standard. Due to the non-volatile nature of QSPI FLASH, it can be used as a
boot device for the system to store the boot image of the system. These
images mainly include FPGA bit files, ARM application code, core application
code and other user data files. The specific models and related parameters of
QSPI FLASH are shown in Table 7-1.
Position
Model
Capacity
Factory
U8
N25Q128
128M Bit
Numonyx
Table 7-1: QSPI FLASH Specification
QSPI FLASH is connected to the dedicated pins of BANK0 and BANK14 of
the FPGA chip. The clock pin is connected to CCLK0 of BANK0, and other data
and chip select signals are connected to D00~D03 and FCS pins of BANK14
respectively. Figure 7-1 shows the hardware connection of QSPI Flash.

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