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MAXREFDES106# Health Sensor Platform 4.0

BioZ Synth Clock

The BioZ drive clock is generated by dividing the output of the

mux by the K Divider. The BioZ drive frequency is generated

by dividing the output of the mux by the K Divider and DAC

OSR.

BioZ ADC Clock

The BioZ ADC Clock is generated by dividing the output of

the mux by the N Divider of the BioZ Receive. The BioZ

ADC Clock sample rate is generated by dividing the output of

the mux by the N Divider and the ADC OSR of the BioZ

Receive.

ECG ADC Clock

The ECG ADC Clock is generated by dividing the PLL

frequency by the F Divider and N Divider of the ECG. The

ECG ADC sample rate is generated by dividing the PLL

frequency by the F Divider, N Divider, and ADC OSR of the

ECG.

To PPG ADC

Frame

The PPG frame rate is generated by the reference clock in the

Clock Selection but is defined under the PPG Settings tab in

the Desired Frame Rate.

PPG Mode Tab

This tab controls the operating mode of the PPG AFE at a high level, and fundamentally switches the

device between two operating modes: Algorithm outputs disabled, and Algorithm outputs enabled.

 The Algorithm disabled mode is used to collect raw PPG data, and the settings are controlled

manually in the PPG settings and ‘PPG Measurement Settings’ tabs instead.

 The Algorithm enabled modes are used to configure the device to enable HR, SpO2, RESP, and

ICG estimation.

With algorithms enabled, a default PPG setup suitable for most situations is loaded and used as input to

the HR, SpO2, RESP, and ICG algorithms. These defaults are intelligently selected, but the evaluation

GUI offers a relatively open interface to modify the input data configuration, if necessary. However, not all

possible configurations are fully supported. If the defaults are modified, ensure the modifications are

properly selected.

Analog Devices MAXREFDES106# User Manual

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