Chapter 5: BIOS Setup
5-20
PCI Express GEN2 Device Register Settings
Target Link Speed [Auto]
IfsupportedbyhardwareandsettoForcetoX.XGT/s,forDownstreamPorts,thissets
anupperlimitonLinkoperationalspeedbyrestrictingthevaluesadvertisedbythe
Upstreamcomponentinitstrainingsequences.WhenAutoisselectedHWinitialized
data will be used.
Congurationoptions:[Auto][Forceto2.5GT/s][Forceto5.0GT/s][Forceto8.0GT/s]
Clock Power Management [Disabled]
IfsupportedbyhardwareandsettoEnabled,thedeviceispermittedtouseCLKREQ#
signalforpowermanagementofLinkclockinaccordancetoprotocoldenedin
appropriateformfactorspecication.
Congurationoptions:[Disabled][Enabled]
Compliance SOS [Disabled]
IfsupportedbyhardwareandsettoEnabled,thiswillforceLTSSMtosendSKP
OrderedSetsbetweensequenceswhensendingCompliancePatternorModied
Compliance Pattern.
Congurationoptions:[Disabled][Enabled]
Hardware Autonomous Width [Enabled]
IfsupportedbyhardwareandsettoDisabled,thiswilldisablethehardware’sabilityto
changelinkwidthexceptforwidthsizereductionforthepurposeofcorrectingunstable
linkoperation.
Congurationoptions:[Disabled][Enabled]
Hardware Autonomous Speed [Enabled]
IfsupportedbyhardwareandsettoDisabled,thiswilldisablethehardware’sability
tochangelinkspeedexceptforspeedratereductionforthepurposeofcorrecting
unstablelinkoperation.
Congurationoptions:[Disabled][Enabled]
PCIE OPROM Slot Options
PCIE1 Slot OpROM [Enabled]
This option allows you to enable or disable the OpROM of the PCIe slots.
Congurationoptions:[Disabled][Enabled]