Bridgetek FT801 - Vertical timing; Signals updating timing control

FT800 Series Programmer Guide
Version 2.1
Document Reference No.: BRT_000030 Clearance No.: BRT#037
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2.2.2 Vertical timing
Figure 3: Vertical Timing
Vertical timing is specified in number of lines. The total number of lines in a frame is
REG_VCYCLE. There are REG_VSIZE rows of pixels in total. They start after
REG_VOFFSET cycles.
Vertical sync timing on signal VSYNC is controlled by REG_VSYNC0 and REG_VSYNC1.
They specify the lines at which VSYNC falls and rises respectively.
2.2.3 Signals updating timing control
With REG_CSPREAD disabled, all color signals are updated at the same time:
Figure 4: Pixel clocking with no CSPREAD
But with REG_CSPREAD enabled, the color signal timings are adjusted slightly so that
fewer signals change simultaneously:
Figure 5: Pixel clocking with CSPREAD