Bridgetek FT801 - Timing example: 480 x272 at 60 Hz

FT800 Series Programmer Guide
Version 2.1
Document Reference No.: BRT_000030 Clearance No.: BRT#037
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2.2.4 Timing example: 480x272 at 60Hz
For a display updating at 60Hz, there are 48000000/60= 800000 fast clocks per frame.
Setting the PCLK divisor REG_PCLK to 5 gives a PCLK frequency of 9.6 MHz and
800000/5= 160000PCLKs per frame.
For a 480 x 272 display, the typical horizontal period is 525 clocks, and vertical period is
286 lines. A little searching shows that a 548 x 292 size gives a period of 160016 clocks,
very close to the target. So with a REG_HCYCLE=548 and REG_VCYCLE=292 the display
frequency is almost exactly 60Hz. The other register settings can be set directly from the
display panel datasheet.