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FT800 Series Programmer Guide
Version 2.1
Document Reference No.: BRT_000030 Clearance No.: BRT#037
44
Product Page
Document Feedback Copyright © Bridgetek Limited
Register Definition 20 REG_DLSWAP Definition
Reserved
31 2 1 0
Address: 0x102450 Reset Value: 0x00
REG_DLSWAP Definition
Note:
R/W
Bit 0 - 1: These bits can be set by the host to validate the display list buffer
of the FT800. The FT800 graphics engine will determine when to render the
screen , depending on what values of these bits are set:
01: Graphics engine will render the screen immediately after current line
is scanned out. It may cause tearing effect.
10: Graphics engine will render the screen immediately after current
frame is scanned out. This is recommended in most of cases.
00: Do not write this value into this register.
11: Do not write this value into this register.
These bits can be also be read by the host to check the availability of the
display list buffer of the FT800. If the value is read as zero, the display list
buffer of the FT800 is safe and ready to write. Otherwise, the host needs to
wait till it becomes zero.

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